llvm-project

AsmParser

[RISCV] Merge GPRPair and GPRF64Pair (#116094 )

2024-11-20 10:08:55 +00:00

Disassembler

[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432 )

2024-11-08 09:12:25 -08:00

GISel

[RISCV] Support f32/f64 libcalls for sin/cos/pow/log/log2/log10/exp/exp2

2024-11-26 23:35:52 -08:00

MCA

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MCTargetDesc

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700 )

2024-11-26 23:39:45 +08:00

TargetInfo

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CMakeLists.txt

[RISCV] Introduce VLOptimizer pass (#108640 )

2024-10-11 09:45:35 -04:00

RISCV.h

[RISCV] Introduce VLOptimizer pass (#108640 )

2024-10-11 09:45:35 -04:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVAsmPrinter.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVCallingConv.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVCallingConv.h

[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503 )

2024-09-06 09:28:33 -07:00

RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVCombine.td

[RISCV] Remove constant_fold_cast_op from RISCVPostLegalizerCombiner.

2024-11-12 23:28:48 -08:00

RISCVConstantPoolValue.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVConstantPoolValue.h

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVDeadRegisterDefinitions.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (#113981 )

2024-10-28 22:37:47 -07:00

RISCVFeatures.td

[RISCV] Support svukte extension (#115657 )

2024-11-27 10:54:57 +08:00

RISCVFrameLowering.cpp

[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605 )

2024-11-25 12:40:37 -08:00

RISCVFrameLowering.h

[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605 )

2024-11-25 12:40:37 -08:00

RISCVGatherScatterLowering.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVGISel.td

[RISCV][GISel] Add atomic load/store test. Add additional atomic load/store isel patterns."

2024-11-20 22:23:18 -08:00

RISCVIndirectBranchTracking.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV][NFC] Remove the unused RISCV_COALESCE_VSETVLI_NAME (#111536 )

2024-10-08 19:53:34 +02:00

RISCVInsertWriteVXRM.cpp

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RISCVInstrFormats.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022 )

2024-10-08 14:09:07 +01:00

RISCVInstrFormatsC.td

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RISCVInstrFormatsV.td

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RISCVInstrGISel.td

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559 )

2024-11-11 20:59:21 -08:00

RISCVInstrInfo.cpp

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700 )

2024-11-26 23:39:45 +08:00

RISCVInstrInfo.h

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889 )

2024-11-25 18:59:31 -08:00

RISCVInstrInfo.td

[RISCV] Use getSignedTargetConstant. NFC

2024-11-18 12:20:44 -08:00

RISCVInstrInfoA.td

[RISCV] Make A implies Zaamo and Zalrsc (#116907 )

2024-11-22 10:35:38 +08:00

RISCVInstrInfoC.td

[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432 )

2024-11-08 09:12:25 -08:00

RISCVInstrInfoD.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoF.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoM.td

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RISCVInstrInfoSFB.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163 )

2024-10-29 21:23:31 -07:00

RISCVInstrInfoV.td

[RISCV] Avoid redundant SchedRead on _TIED VPseudos (#113940 )

2024-10-29 10:49:35 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Use getSignedTargetConstant. NFC

2024-11-18 12:20:44 -08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC

2024-11-08 18:11:39 -08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Use integer VTypeInfo predicate for vmv_v_v_vl pattern (#114915 )

2024-11-05 13:01:36 +08:00

RISCVInstrInfoXCV.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163 )

2024-10-29 21:23:31 -07:00

RISCVInstrInfoXSf.td

[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274 )

2024-10-30 11:52:49 -07:00

RISCVInstrInfoXTHead.td

[RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.

2024-11-19 21:41:14 -08:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

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RISCVInstrInfoZa.td

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RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

[RISCV] Use the OperandTransform field of a couple PatLeafs to simplify isel patterns. NFC

2024-11-18 16:37:48 -08:00

RISCVInstrInfoZc.td

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446 )

2024-09-26 22:56:12 -07:00

RISCVInstrInfoZcmop.td

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RISCVInstrInfoZfa.td

[RISCV] Add OperandType to loadfpimm. (#114150 )

2024-10-29 19:42:35 -07:00

RISCVInstrInfoZfbfmin.td

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RISCVInstrInfoZfh.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

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RISCVInstrInfoZk.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279 )

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZvfbf.td

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RISCVInstrInfoZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317 )

2024-10-31 10:21:14 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Merge GPRPair and GPRF64Pair (#116094 )

2024-11-20 10:08:55 +00:00

RISCVISelDAGToDAG.h

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284 )

2024-09-11 21:13:26 -07:00

RISCVISelLowering.cpp

[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633 )

2024-11-25 16:12:45 -08:00

RISCVISelLowering.h

[RISCV] Add an implementation of findRepresentativeClass to assign i32 to GPRRegClass for RV64. (#116165 )

2024-11-18 10:07:20 -08:00

RISCVLandingPadSetup.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

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RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVMergeBaseOffset.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

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RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVProcessors.td

[RISCV] Add mvendorid/marchid/mimpid to CPU definitions (#116202 )

2024-11-22 22:58:54 +08:00

RISCVProfiles.td

[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942 )

2024-11-10 07:18:05 +00:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV] Fix a warning

2024-11-25 12:57:05 -08:00

RISCVRegisterInfo.h

[RISCV] Correct the precedence in isVRegClass (#116579 )

2024-11-18 18:12:57 +08:00

RISCVRegisterInfo.td

[RISCV] Merge GPRPair and GPRF64Pair (#116094 )

2024-11-20 10:08:55 +00:00

RISCVSchedRocket.td

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RISCVSchedSiFive7.td

[llvm][NFC] Fix typos: replace “avaliable” with “available” across various files (#114524 )

2024-11-01 13:25:04 +00:00

RISCVSchedSiFiveP400.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893 )

2024-11-21 10:59:46 -08:00

RISCVSchedSiFiveP600.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893 )

2024-11-21 10:59:46 -08:00

RISCVSchedSyntacoreSCR1.td

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RISCVSchedSyntacoreSCR7.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVSchedSyntacoreSCR345.td

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RISCVSchedule.td

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RISCVScheduleV.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009 )

2024-10-28 09:37:54 -07:00

RISCVScheduleXSf.td

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RISCVScheduleZb.td

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RISCVScheduleZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317 )

2024-10-31 10:21:14 -07:00

RISCVSchedXiangShanNanHu.td

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RISCVSubtarget.cpp

[RISCV] Remove getPostRAMutations (#117527 )

2024-11-26 10:55:43 +08:00

RISCVSubtarget.h

[RISCV] Remove getPostRAMutations (#117527 )

2024-11-26 10:55:43 +08:00

RISCVSystemOperands.td

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RISCVTargetMachine.cpp

[RISCV] Enable global merging by default (#115495 )

2024-11-15 13:22:34 +00:00

RISCVTargetMachine.h

Overhaul the TargetMachine and LLVMTargetMachine Classes (#111234 )

2024-11-14 13:30:05 -08:00

RISCVTargetObjectFile.cpp

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

[RISCV][CostModel] add cost for cttz/ctlz under the non-zvbb (#117515 )

2024-11-26 11:40:52 +08:00

RISCVTargetTransformInfo.h

[llvm] Add BasicTTIImpl::areInlineCompatible for target feature subset checks (#117493 )

2024-11-25 11:22:49 +08:00

RISCVVectorPeephole.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVVLOptimizer.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVZacasABIFix.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00