318c69de52
The issue with slow compile-time was caused by an assert in AArch64RegisterInfo.cpp. The assert invokes 'checkAllSuperRegsMarked' after adding all the reserved registers. This call gets very expensive after adding the _HI registers due to the way the function searches in the 'Exception' list, which is expected to be a small list but isn't (the patch added 190 _HI regs). It was possible to rewrite the code in such a way that the _HI registers are marked as reserved after the check. This makes the problem go away entirely and restores compile-time to what it was before (tested for `check-runtimes`, which previously showed a ~5x slowdown). This reverts commits: 1434d2ab215e3ea9c5f34689d056edd3d4423a78 2704647fb7986673b89cef1def729e3b022e2607
153 lines
6.3 KiB
C++
153 lines
6.3 KiB
C++
#include "AArch64RegisterInfo.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "gtest/gtest.h"
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#define GET_COMPUTE_FEATURES
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#include "AArch64GenInstrInfo.inc"
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using namespace llvm;
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namespace {
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std::unique_ptr<TargetMachine> createTargetMachine(const std::string &CPU) {
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auto TT(Triple::normalize("aarch64--"));
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LLVMInitializeAArch64TargetInfo();
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LLVMInitializeAArch64Target();
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LLVMInitializeAArch64TargetMC();
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std::string Error;
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const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
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return std::unique_ptr<TargetMachine>(
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TheTarget->createTargetMachine(TT, CPU, "", TargetOptions(), std::nullopt,
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std::nullopt, CodeGenOptLevel::Default));
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}
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std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
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AArch64Subtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM, true);
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return std::make_unique<AArch64InstrInfo>(ST);
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}
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TEST(AArch64LaneBitmasks, SubRegs) {
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std::unique_ptr<TargetMachine> TM = createTargetMachine("");
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ASSERT_TRUE(TM);
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std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
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ASSERT_TRUE(II);
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const AArch64RegisterInfo &TRI = II->getRegisterInfo();
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// Test that the lane masks for the subregisters 'bsub, hsub, ssub, etc'
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// are composed correctly.
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
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TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::hsub));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
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TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::ssub));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
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TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::dsub));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
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TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::zsub));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
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TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::zsub0));
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// Test that the lane masks for tuples are composed correctly.
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
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TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
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TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
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TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::dsub1));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
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TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
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TRI.getSubRegIndexLaneMask(AArch64::qsub1));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
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TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
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TRI.getSubRegIndexLaneMask(AArch64::sube64));
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
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TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
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TRI.getSubRegIndexLaneMask(AArch64::subo64));
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// Test that there is no overlap between different (sub)registers
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// in a tuple.
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
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TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
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TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
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TRI.getSubRegIndexLaneMask(AArch64::dsub3),
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LaneBitmask::getNone());
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
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TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
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TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
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TRI.getSubRegIndexLaneMask(AArch64::qsub3),
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LaneBitmask::getNone());
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
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TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
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TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
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TRI.getSubRegIndexLaneMask(AArch64::zsub3),
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LaneBitmask::getNone());
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
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TRI.getSubRegIndexLaneMask(AArch64::subo32),
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LaneBitmask::getNone());
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EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
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TRI.getSubRegIndexLaneMask(AArch64::subo64),
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LaneBitmask::getNone());
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// Test that getting a subregister results in the expected subregister.
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::bsub), AArch64::B0);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::hsub), AArch64::H0);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::ssub), AArch64::S0);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub), AArch64::D0);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub),
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AArch64::B8);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub),
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AArch64::H8);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub),
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AArch64::S8);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
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EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
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EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
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EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
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EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
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EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32),
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AArch64::W1);
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}
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} // namespace
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