llvm-project

AsmParser

[RISCV] Call updateCZceFeatureImplications from RISCVAsmParser::setFeatureBits. (#179870 )

2026-02-05 07:03:26 -08:00

Disassembler

[RISCV] Use decodeVMaskReg for VMaskCarryInOp. NFC (#177742 )

2026-01-25 00:41:16 +00:00

GISel

[perf] Replace copy-assign by move-assign in llvm/lib/Target (#179464 )

2026-02-04 13:47:01 +00:00

MCA

[RISCV] Rename nf->nfields in MC layer. NFC (#179365 )

2026-02-02 22:29:24 -08:00

MCTargetDesc

[RISCV] Add C/Zcf/Zcd/Zce implication rules to subtarget construction. (#179615 )

2026-02-04 09:32:11 -08:00

TargetInfo

[RISCV] Add initial assembler/MC layer support for big-endian (#146534 )

2025-08-22 09:21:10 +02:00

CMakeLists.txt

[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis

2026-01-12 12:00:55 +08:00

RISCV.h

[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640 )

2025-11-21 05:04:05 +00:00

RISCV.td

[RISCV] Rename Tenstorrent Ascalon D8 to Ascalon X (#178199 )

2026-01-27 21:31:51 +00:00

RISCVAsmPrinter.cpp

[RISC-V][Mach-O] Add assembler support for Mach-O relocations. (#177446 )

2026-01-26 14:06:30 -08:00

RISCVCallingConv.cpp

[RISCV][llvm] Handle calling convention for P extension fixed vectors (#176093 )

2026-01-19 12:09:27 +08:00

RISCVCallingConv.h

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RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

[RISCV] Remove last use of @llvm.experimental.vp.splat in RISCVCodeGenPrepare. NFCI (#170543 )

2025-12-08 06:09:03 +00:00

RISCVCombine.td

[RISCV][GISel] Fold G_FCONSTANT 0.0 store into G_CONSTANT x0 (#163008 )

2025-10-23 15:50:04 +08:00

RISCVConstantPoolValue.cpp

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RISCVConstantPoolValue.h

[Target] Add "override" where appropriate (NFC) (#165083 )

2025-10-25 06:23:43 -07:00

RISCVDeadRegisterDefinitions.cpp

CodeGen: Remove TRI argument from getRegClass (#158225 )

2025-11-10 15:43:55 -08:00

RISCVExpandAtomicPseudoInsts.cpp

[RISCV] 'Zalrsc' may permit non-base instructions (#165042 )

2025-10-28 12:51:11 -07:00

RISCVExpandPseudoInsts.cpp

[RISCV] Add short forward branch support for qc.e.lb(u), qc.e.lh(u) and qc.e.lw (#172629 )

2025-12-18 09:38:31 +05:30

RISCVFeatures.td

[RISCV] Introduce a new syntax for processor-specific tuning feature strings (#175063 )

2026-02-05 15:22:07 -08:00

RISCVFoldMemOffset.cpp

[RISCV] Add Zilsd to RISCVFoldMemOffset (#176544 )

2026-01-19 11:19:30 +05:30

RISCVFrameLowering.cpp

[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581 )

2026-01-13 08:21:58 +05:30

RISCVFrameLowering.h

[CodeGen] Replace (Min,Max)CSFrameIndex with flag on frame object [NFCI] (#170905 )

2025-12-06 14:00:55 -08:00

RISCVGatherScatterLowering.cpp

[IR] Replace alignment argument with attribute on masked intrinsics (#163802 )

2025-10-20 08:50:09 +00:00

RISCVGISel.td

[RISCV][NFC] Simplify Imm range checks (#170497 )

2025-12-04 06:04:49 +01:00

RISCVIndirectBranchTracking.cpp

[RISCV] Emit lpad for function with returns-twice attribute (#170520 )

2025-12-04 13:25:57 +08:00

RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis

2026-01-12 12:00:55 +08:00

RISCVInsertWriteVXRM.cpp

[llvm] Use "= default" (NFC) (#166088 )

2025-11-02 17:16:47 -08:00

RISCVInstrFormats.td

[RISCV] Simplify how RVVConstraints are declared in tablegen. NFC (#178972 )

2026-01-31 08:55:42 -08:00

RISCVInstrFormatsC.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325 )

2026-01-27 22:55:47 -08:00

RISCVInstrFormatsV.td

[RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVInstrFormatsV.td. NFC (#179348 )

2026-02-03 07:06:25 -08:00

RISCVInstrFormatsXAIF.td

[RISCV] AI Foundry ET extensions for RISC-V (#174571 )

2026-01-13 12:54:11 -08:00

RISCVInstrGISel.td

[GISel] Add G_CTLS Opcode and combines, lower to cls(w) (#175069 )

2026-01-16 13:22:18 -08:00

RISCVInstrInfo.cpp

[CodeGen][TII] Delete analyzeSelect hook (#175828 )

2026-02-04 14:14:45 -08:00

RISCVInstrInfo.h

[CodeGen][TII] Delete analyzeSelect hook (#175828 )

2026-02-04 14:14:45 -08:00

RISCVInstrInfo.td

[RISCV] Enable SelectCompressOpt with HasStdExtZca. (#179601 )

2026-02-03 21:56:48 -08:00

RISCVInstrInfoA.td

[RISCV] Use GPR instead of ixlenimm for sextshamt in PseudoMaskedAMOMinMax. NFC (#171736 )

2025-12-10 20:43:46 -08:00

RISCVInstrInfoC.td

[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762 )

2026-02-04 13:00:21 -08:00

RISCVInstrInfoD.td

[RISCV] Fix fcanonicalize for Z*inx (#175984 )

2026-01-15 23:03:38 -08:00

RISCVInstrInfoF.td

[RISCV] Use IntImmLeaf/FPImmLeaf. NFC (#178525 )

2026-01-28 15:40:37 -08:00

RISCVInstrInfoM.td

[RISCV][NFC] Cleanup Negative Predicate Names (#155017 )

2025-08-22 14:46:41 -07:00

RISCVInstrInfoP.td

[RISCV] Use addd/subd for i64 add/sub for RV32+P. (#180129 )

2026-02-06 12:42:11 -08:00

RISCVInstrInfoQ.td

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RISCVInstrInfoSFB.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902 )

2026-01-14 10:22:47 -08:00

RISCVInstrInfoV.td

[RISCV] Sink some encoding related lets into class/def bodies. NFC (#179544 )

2026-02-03 15:05:35 -08:00

RISCVInstrInfoVPseudos.td

[RISCV] Rename VUnitStrideLoadMask->VUnitStrideMaskLoad. NFC (#179360 )

2026-02-02 22:31:26 -08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Rename VUnitStrideLoadMask->VUnitStrideMaskLoad. NFC (#179360 )

2026-02-02 22:31:26 -08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Add missing HasStdExtZvkb Predicate to some of the vector rotate patterns. NFC (#178250 )

2026-01-27 19:30:54 -08:00

RISCVInstrInfoXAIF.td

[RISCV] AI Foundry ET extensions for RISC-V (#174571 )

2026-01-13 12:54:11 -08:00

RISCVInstrInfoXAndes.td

[RISCV] Use IntImmLeaf/FPImmLeaf. NFC (#178525 )

2026-01-28 15:40:37 -08:00

RISCVInstrInfoXCV.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902 )

2026-01-14 10:22:47 -08:00

RISCVInstrInfoXMips.td

[RISC-V] Reduce code duplication for uimm*_lsb* operands. NFC

2026-01-25 21:45:00 -08:00

RISCVInstrInfoXqccmp.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325 )

2026-01-27 22:55:47 -08:00

RISCVInstrInfoXqci.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325 )

2026-01-27 22:55:47 -08:00

RISCVInstrInfoXRivos.td

[RISCV] Rename RVInstV->RVInstVUnary. NFC (#177900 )

2026-01-26 13:54:02 -08:00

RISCVInstrInfoXSf.td

[RISCV] Add tied destination constraint to CustomSiFiveVMACC. (#179567 )

2026-02-04 17:58:07 +00:00

RISCVInstrInfoXSfmm.td

[RISCV] Use inheritance to simplify RVInstSet*VL* classes. NFC (#177797 )

2026-01-25 20:32:06 -08:00

RISCVInstrInfoXSpacemiT.td

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RISCVInstrInfoXTHead.td

[RISCV] Use TargetConstant for the immediate RISCVISD::SHL_ADD nodes. (#166312 )

2025-11-04 09:56:59 -08:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325 )

2026-01-27 22:55:47 -08:00

RISCVInstrInfoZa.td

[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411 )

2025-10-07 22:24:52 -07:00

RISCVInstrInfoZalasr.td

[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995 )

2025-10-07 21:30:09 -07:00

RISCVInstrInfoZb.td

[RISCV] Add ISEL pattern to convert add (shl -1, X), Y to sub Y, (bset zero, X) (#178601 )

2026-01-29 15:11:21 +05:30

RISCVInstrInfoZc.td

[RISCV] Add OPC_C0/C1/C2 named values to tablegen. NFC (#178325 )

2026-01-27 22:55:47 -08:00

RISCVInstrInfoZclsd.td

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RISCVInstrInfoZcmop.td

[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609 )

2026-02-03 23:39:53 +08:00

RISCVInstrInfoZfa.td

[RISCV] Remove decodeRTZArg. NFC (#177744 )

2026-01-24 11:08:57 -08:00

RISCVInstrInfoZfbfmin.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902 )

2026-01-14 10:22:47 -08:00

RISCVInstrInfoZfh.td

[RISCV] Fix fcanonicalize for Z*inx (#175984 )

2026-01-15 23:03:38 -08:00

RISCVInstrInfoZibi.td

[RISCV][NFC] Push riscv_selectcc PatFrag Inwards (#175902 )

2026-01-14 10:22:47 -08:00

RISCVInstrInfoZicbo.td

[RISCV][NFC] Cleanup Negative Predicate Names (#155017 )

2025-08-22 14:46:41 -07:00

RISCVInstrInfoZicfiss.td

[RISCV] Make MOP/HINT-based instruction mnemonics always available (#178609 )

2026-02-03 23:39:53 +08:00

RISCVInstrInfoZicond.td

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RISCVInstrInfoZilsd.td

[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640 )

2025-11-21 05:04:05 +00:00

RISCVInstrInfoZimop.td

[RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289 )

2025-08-25 14:06:28 -07:00

RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

[RISCV] Remove unnecessary 'let' from VFWMACCBF16_V. NFC (#178367 )

2026-01-27 22:56:07 -08:00

RISCVInstrInfoZvfofp8min.td

[llvm][RISCV] Support Zvfofp8min llvm intrinsics and codegen (#172585 )

2025-12-24 02:59:25 +00:00

RISCVInstrInfoZvk.td

[RISCV] Add isel patterns to form vwsll.vx/vi when the LHS is an any_extend. (#179571 )

2026-02-03 19:22:00 -08:00

RISCVInstrInfoZvqdotq.td

[RISCV] Correct the Predicates for Zvqdotq patterns. NFC (#178295 )

2026-01-27 14:39:56 -08:00

RISCVInstrPredicates.td

[RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well (#172111 )

2025-12-16 22:32:20 +00:00

RISCVInterleavedAccess.cpp

[IR] Replace alignment argument with attribute on masked intrinsics (#163802 )

2025-10-20 08:50:09 +00:00

RISCVISelDAGToDAG.cpp

[RISCV] Use addd/subd for i64 add/sub for RV32+P. (#180129 )

2026-02-06 12:42:11 -08:00

RISCVISelDAGToDAG.h

[RISCV] Support XSfmm LLVM IR and CodeGen (#143069 )

2025-10-14 02:01:57 +00:00

RISCVISelLowering.cpp

[RISCV] Use addd/subd for i64 add/sub for RV32+P. (#180129 )

2026-02-06 12:42:11 -08:00

RISCVISelLowering.h

[CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC) (#175844 )

2026-02-02 17:40:02 -08:00

RISCVLandingPadSetup.cpp

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RISCVLateBranchOpt.cpp

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RISCVLoadStoreOptimizer.cpp

[NFC][MI] Tidy Up RegState enum use (2/2) (#177090 )

2026-01-23 00:19:03 -08:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

[Target] Add "override" where appropriate (NFC) (#165083 )

2025-10-25 06:23:43 -07:00

RISCVMachineScheduler.cpp

[RISCV] Schedule RVV instructions with compatible vtype/vl first

2026-01-12 12:02:39 +08:00

RISCVMachineScheduler.h

[RISCV] Schedule RVV instructions with compatible vtype/vl first

2026-01-12 12:02:39 +08:00

RISCVMacroFusion.td

[RISCV] Add macro fusion support for spacemit-x100 (#178594 )

2026-02-04 14:25:52 +08:00

RISCVMakeCompressible.cpp

[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762 )

2026-02-04 13:00:21 -08:00

RISCVMergeBaseOffset.cpp

[RISCV] Detect QC_E_ADDAI and fold in RISCVMergeBaseOffset (#175496 )

2026-01-12 22:43:38 +05:30

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542 )

2026-01-06 17:03:23 -08:00

RISCVPassRegistry.def

[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381 )

2025-11-19 06:51:18 +00:00

RISCVPfmCounters.td

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RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Introduce a new syntax for processor-specific tuning feature strings (#175063 )

2026-02-05 15:22:07 -08:00

RISCVProfiles.td

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RISCVPromoteConstant.cpp

[RISCV] Introduce pass to promote double constants to a global array (#160536 )

2025-11-05 14:31:17 +00:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920 )

2026-01-09 14:00:53 +08:00

RISCVRegisterInfo.cpp

[RISCV] Add ZZZ_ to some inline assembly vector register classes to sort them after VR/VRNoV0 in regclass enum. (#177087 )

2026-01-21 21:23:06 -08:00

RISCVRegisterInfo.h

[RegAlloc] Change the computation of CSRCost (#177226 )

2026-02-04 10:08:57 -08:00

RISCVRegisterInfo.td

[RISCV] Add a template function for disassembling LMUL=2/4/8 vector registers. NFC (#177681 )

2026-01-23 15:58:55 -08:00

RISCVSchedAndes45.td

[RISCV] Update Andes45 vector integer arithmetic scheduling info (#174538 )

2026-02-05 13:07:33 +08:00

RISCVSchedGenericOOO.td

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RISCVSchedMIPSP8700.td

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RISCVSchedRocket.td

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RISCVSchedSiFive7.td

[RISCV] LMUL lists for indexed and strided loads (#169756 )

2025-12-05 13:10:22 -08:00

RISCVSchedSiFiveP400.td

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RISCVSchedSiFiveP500.td

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RISCVSchedSiFiveP600.td

[RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562 )

2025-12-10 13:59:13 +08:00

RISCVSchedSiFiveP800.td

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RISCVSchedSpacemitX60.td

[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556 )

2025-12-18 07:04:42 -08:00

RISCVSchedSyntacoreSCR1.td

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RISCVSchedSyntacoreSCR7.td

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RISCVSchedSyntacoreSCR345.td

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RISCVSchedTTAscalonX.td

[RISCV] Rename Tenstorrent Ascalon D8 to Ascalon X (#178199 )

2026-01-27 21:31:51 +00:00

RISCVSchedule.td

[RISCV] Assign separate latencies for vector COPYs in SpacemitX60 scheduling model (#172556 )

2025-12-18 07:04:42 -08:00

RISCVScheduleV.td

[RISCV] LMUL lists for indexed and strided loads (#169756 )

2025-12-05 13:10:22 -08:00

RISCVScheduleXSf.td

[RISCV] Add LLVM IR intrinsics and codegen for XSfvfexp* and XSfvfexpa* (#164499 )

2025-10-24 18:09:03 +00:00

RISCVScheduleZb.td

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RISCVScheduleZvk.td

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RISCVSchedXiangShanNanHu.td

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RISCVSelectionDAGInfo.cpp

[SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125 )

2025-11-16 18:26:03 +03:00

RISCVSelectionDAGInfo.h

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RISCVSubtarget.cpp

[RISCV] Add C/Zcf/Zcd/Zce implication rules to subtarget construction. (#179615 )

2026-02-04 09:32:11 -08:00

RISCVSubtarget.h

[RISCV] Deprecate RISCVSubtarget::hasStdExtCOrZcd() and hasStdExtCOrZcfOrZce(). (#179762 )

2026-02-04 13:00:21 -08:00

RISCVSystemOperands.td

[RISCV] AI Foundry ET extensions for RISC-V (#174571 )

2026-01-13 12:54:11 -08:00

RISCVTargetMachine.cpp

[RISCV] Run VLOptimizer right after ISel (#179377 )

2026-02-03 22:15:41 -08:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[RISC-V][Mach-O] Add codegen support for Mach-O object format. (#178263 )

2026-02-02 14:11:27 -08:00

RISCVTargetObjectFile.h

[RISC-V][Mach-O] Add codegen support for Mach-O object format. (#178263 )

2026-02-02 14:11:27 -08:00

RISCVTargetTransformInfo.cpp

[LV] Add support for llvm.vector.partial.reduce.fadd (#163975 )

2026-01-28 15:05:34 +00:00

RISCVTargetTransformInfo.h

[LV] Add support for llvm.vector.partial.reduce.fadd (#163975 )

2026-01-28 15:05:34 +00:00

RISCVVectorMaskDAGMutation.cpp

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RISCVVectorPeephole.cpp

[RISCV] Fold vmerge into op with undef passthru by using vmerge's vl (#179862 )

2026-02-06 00:13:14 +08:00

RISCVVLOptimizer.cpp

[RISCV] Only reduce VLs of instructions with demanded VLs (#168693 )

2025-11-20 03:49:59 +00:00

RISCVVMV0Elimination.cpp

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RISCVVSETVLIInfoAnalysis.cpp

[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis

2026-01-12 12:00:55 +08:00

RISCVVSETVLIInfoAnalysis.h

[RISCV][NFC] Add RISCVVSETVLIInfoAnalysis

2026-01-12 12:00:55 +08:00

RISCVZacasABIFix.cpp

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RISCVZilsdOptimizer.cpp

[llvm][RISCV] Make X0 register pair legal in pre-ra pass (#169164 )

2026-01-21 14:13:44 +08:00