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llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
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Sam Tebbs 6b19a546aa
[LV] Bundle partial reductions inside VPExpressionRecipe (#147302) 
This PR bundles partial reductions inside the VPExpressionRecipe class.

Stacked PRs:
1. https://github.com/llvm/llvm-project/pull/147026
2. https://github.com/llvm/llvm-project/pull/147255
3. https://github.com/llvm/llvm-project/pull/156976
4. https://github.com/llvm/llvm-project/pull/160154
5. -> https://github.com/llvm/llvm-project/pull/147302
6. https://github.com/llvm/llvm-project/pull/162503
7. https://github.com/llvm/llvm-project/pull/147513
2025-10-23 11:18:55 +00:00
..
bf16.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
blend-any-of-reduction-cost.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
blocks-with-dead-instructions.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
dead-ops-cost.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
defaults.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
divrem.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
evl-compatible-loops.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
f16.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
first-order-recurrence-scalable-vf1.ll
[VPlan] Add dedicated user for resume phi with epilogue vectorization.
2025-08-10 21:21:16 +01:00
fminimumnum.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
force-vect-msg.ll
[LV][RISCV] Try fixing Windows buildbot failure in force-vect-msg.ll. NFC
2025-08-09 21:09:36 +08:00
gather-scatter-cost.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
illegal-type.ll
[VPlan] Don't access canonical IV in VPWidenPointerInduction::execute.
2025-03-15 21:32:48 +00:00
induction-costs.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
inloop-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
interleaved-accesses-zve32x.ll
…
interleaved-accesses.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
interleaved-cost.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
interleaved-masked-access.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
interleaved-store-with-gap.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
lit.local.cfg
…
lmul.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
low-trip-count.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
mask-index-type.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
masked_gather_scatter.ll
[VPlan] Run CSE closer to VPlan::execute. (#160572)
2025-09-26 09:38:58 +00:00
only-compute-cost-for-vplan-vfs.ll
[VPlan] Support VPWidenPointerInductionRecipes with EVL tail folding (#152110)
2025-08-07 10:54:24 +08:00
ordered-reduction.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
partial-reduce-dot-product.ll
[LV] Bundle partial reductions inside VPExpressionRecipe (#147302)
2025-10-23 11:18:55 +00:00
pr87378-vpinstruction-or-drop-poison-generating-flags.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
pr88802.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
pr154103.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
preserve-dbg-loc.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
reductions.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
reg-usage-bf16.ll
[VPlan] Always consider register pressure on RISC-V (#156951)
2025-09-12 06:21:54 +00:00
reg-usage-f16.ll
[VPlan] Always consider register pressure on RISC-V (#156951)
2025-09-12 06:21:54 +00:00
reg-usage-maxbandwidth.ll
[LV][VPlan] Reduce register usage of VPEVLBasedIVPHIRecipe. (#154482)
2025-08-21 07:39:01 +08:00
reg-usage-prune-vf.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
reg-usage.ll
[VPlan] Always consider register pressure on RISC-V (#156951)
2025-09-12 06:21:54 +00:00
remark-reductions.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
riscv-interleaved.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
riscv-unroll.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
riscv-vector-reverse.ll
[VPlan] Add VPInstruction to unpack vector values to scalars. (#155670)
2025-10-19 18:49:05 +00:00
safe-dep-distance.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
scalable-basics.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
scalable-tailfold.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
scalable-vf-hint.ll
…
select-cmp-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
select-invariant-cond-cost.ll
…
short-trip-count.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
strided-accesses.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
tail-folding-bin-unary-ops-args.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
tail-folding-call-intrinsics.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
tail-folding-cast-intrinsics.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-cond-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-cost.ll
[RISCV][LV] Remove redundant -force-tail-folding-style from tests. NFC
2025-07-28 16:11:01 +08:00
tail-folding-div.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-fixed-order-recurrence.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-gather-scatter.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
tail-folding-inloop-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-interleave.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
tail-folding-intermediate-store.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
tail-folding-iv32.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-known-no-overflow.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-masked-loadstore.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
tail-folding-no-masking.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-ordered-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-reduction-cost.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-reduction.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-reverse-load-store.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
tail-folding-safe-dep-distance.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
tail-folding-uniform-store.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
truncate-to-minimal-bitwidth-cost.ll
[LV] Check for TruncInsts in canTruncateToMinimalBitwidth.
2025-10-20 22:31:16 +01:00
truncate-to-minimal-bitwidth-evl-crash.ll
[VPlan] Set flags when constructing truncs using VPWidenCastRecipe.
2025-10-12 14:01:12 +01:00
type-info-cache-evl-crash.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
uniform-load-store.ll
[IR] Replace alignment argument with attribute on masked intrinsics (#163802)
2025-10-20 08:50:09 +00:00
unroll-in-loop-vectorizer.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
veclib-function-calls.ll
[IR] Mark vector intrinsics speculatable (#162334)
2025-10-09 09:41:59 +01:00
vector-loop-backedge-elimination-with-evl.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
vectorize-vp-intrinsics.ll
[VPlan] Remove original loop blocks if dead. (#155497)
2025-10-01 16:53:59 +00:00
vf-will-not-generate-any-vector-insts.ll
[LV][EVL] Remove metadata on EVL vectorized loops (#155760)
2025-09-23 07:39:33 +08:00
vplan-riscv-vector-reverse.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
vplan-vp-call-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-cast-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-fixed-order-recurrence.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
zvl32b.ll
…