6b2cca7f8f
This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770
59 lines
1.8 KiB
C++
59 lines
1.8 KiB
C++
//===-- RISCVMCTargetDesc.h - RISCV Target Descriptions ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISCV specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Config/config.h"
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class StringRef;
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class Target;
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class Triple;
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class raw_ostream;
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class raw_pwrite_stream;
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Target &getTheRISCV32Target();
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Target &getTheRISCV64Target();
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MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options);
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MCObjectWriter *createRISCVELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
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bool Is64Bit);
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}
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// Defines symbolic names for RISC-V registers.
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#define GET_REGINFO_ENUM
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#include "RISCVGenRegisterInfo.inc"
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// Defines symbolic names for RISC-V instructions.
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#define GET_INSTRINFO_ENUM
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#include "RISCVGenInstrInfo.inc"
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#endif
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