3a8d108b2b
The bug arises during register allocation on i686 for CMPXCHG8B instruction when base pointer is needed. CMPXCHG8B needs 4 implicit registers (EAX, EBX, ECX, EDX) and a memory address, plus ESI is reserved as the base pointer. With such constraints the only way register allocator would do its job successfully is when the addressing mode of the instruction requires only one register. If that is not the case - we are emitting additional LEA instruction to compute the address. It fixes PR28755. Patch by Alexander Ivchenko <alexander.ivchenko@intel.com> Differential Revision: https://reviews.llvm.org/D25088 llvm-svn: 287875
36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=x86 -stackrealign -O2 | FileCheck %s
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; PR28755
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; Check that register allocator is able to handle that
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; a-lot-of-fixed-and-reserved-registers case. We do that by
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; emmiting lea before 4 cmpxchg8b operands generators.
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define void @foo_alloca(i64* %a, i32 %off, i32 %n) {
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%dummy = alloca i32, i32 %n
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%addr = getelementptr inbounds i64, i64* %a, i32 %off
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%res = cmpxchg i64* %addr, i64 0, i64 1 monotonic monotonic
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ret void
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}
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; CHECK-LABEL: foo_alloca
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; CHECK: leal {{\(%e..,%e..,.*\)}}, [[REGISTER:%e.i]]
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: movl $1, %ebx
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; CHECK-NEXT: lock cmpxchg8b ([[REGISTER]])
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; If we don't use index register in the address mode -
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; check that we did not generate the lea.
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define void @foo_alloca_direct_address(i64* %addr, i32 %n) {
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%dummy = alloca i32, i32 %n
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%res = cmpxchg i64* %addr, i64 0, i64 1 monotonic monotonic
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ret void
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}
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; CHECK-LABEL: foo_alloca_direct_address
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; CHECK-NOT: leal {{\(%e.*\)}}, [[REGISTER:%e.i]]
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; CHECK: lock cmpxchg8b ([[REGISTER]])
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