llvm-project

History

Tim Northover c08db1840c ARM: fix handling of SUB immediates in peephole opt.

We were negating an immediate that was going to be used in a SUBri form
unnecessarily. Since ADD/SUB are very similar we *can* do that, but we have to
change the SUB to an ADD at the same time. This also applies to ADD, and allows
us to handle a slightly larger range of immediates for those two operations.

rdar://25992245

llvm-svn: 268276

2016-05-02 18:30:08 +00:00

AArch64

[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()

2016-03-31 20:53:47 +00:00

AMDGPU

When printing MIR, output to errs() rather than outs().

2016-02-19 00:18:46 +00:00

ARM

ARM: fix handling of SUB immediates in peephole opt.

2016-05-02 18:30:08 +00:00

Generic

When printing MIR, output to errs() rather than outs().