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llvm-project/llvm/test/CodeGen
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Muhammad Omair Javaid 32bd1f562f Revert "[SVE] Add patterns for shift intrinsics with FalseLanesZero mode" 
This reverts commit 22c3ba4bb519e12395c676ffe436ea4b8400234a.

Breaks buildbot https://lab.llvm.org/buildbot/#/builders/197/builds/4272

Differential Revision: https://reviews.llvm.org/D145551
2023-03-20 12:39:39 +05:00
..
AArch64
Revert "[SVE] Add patterns for shift intrinsics with FalseLanesZero mode"
2023-03-20 12:39:39 +05:00
AMDGPU
[AMDGPU] Reserve extra SGPR blocks wth XNACK "any" TID Setting
2023-03-17 20:26:23 -07:00
ARC
…
ARM
Remove -lower-global-dtors-via-cxa-atexit flag
2023-03-14 14:18:11 -07:00
AVR
[AVR] Fix incorrect flags of livein registers when spilling them
2023-02-28 11:08:54 +08:00
BPF
[BPF] Improve pruning to avoid generate more types in BTF
2023-03-13 09:34:37 -07:00
CSKY
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DirectX
[NFC] Fix missing colon in CHECK directives
2023-02-21 00:13:04 +05:30
Generic
Revert "DwarfEHPrepare: insert extra unwind paths for stack protector to instrument"
2023-03-16 11:55:53 +00:00
Hexagon
[Hexagon] Ensure proper ordering of instructions in HVC::AlignVectors
2023-03-17 08:13:49 -07:00
Inputs
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Lanai
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LoongArch
[LoongArch] Emit bytepick for picking from concatenation of two values
2023-03-16 15:07:06 +08:00
M68k
[M68k] Add support for basic memory constraints in inline asm
2023-03-08 13:52:34 -08:00
Mips
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
MIR
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MLRegalloc
Specify target triple for bb-prefix-dump.ll
2023-02-11 14:02:44 -08:00
MSP430
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NVPTX
[NVPTX] Report fatal error on empty argument type.
2023-03-18 01:27:43 +01:00
PowerPC
[SCEVExpander] Always use scevgep as name
2023-03-17 14:27:03 +01:00
RISCV
[RISCV] Add isReMaterializable to FLI instructions.
2023-03-17 12:16:37 -07:00
SPARC
Revert "[SPARC] Lower BR_CC to BPr on 64-bit target whenever possible"
2023-03-12 04:20:25 -04:00
SPIRV
[SPIR-V] Promote arbitrary width ints to regular width
2023-03-13 22:44:47 +01:00
SystemZ
[SCEVExpander] Always use scevgep as name
2023-03-17 14:27:03 +01:00
Thumb
[LSR] Improve filtered uses in NarrowSearchSpaceByPickingWinnerRegs
2023-02-16 15:48:12 +00:00
Thumb2
[Codegen][ARM][AArch64] Support symmetric operations on complex numbers
2023-03-14 12:11:10 +00:00
VE
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
WebAssembly
[WebAssembly] Replace Bugzilla links with Github issues
2023-03-17 20:13:00 -07:00
WinCFGuard
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WinEH
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X86
CodeGen: Reorder case handling for is.fpclass legalization
2023-03-17 11:29:50 -04:00
XCore
[XCore] Adapt threads.ll to opaque pointers.
2023-02-15 10:43:51 +00:00