237 lines
14 KiB
LLVM
237 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph\:" --version 5
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; REQUIRES: asserts
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; RUN: opt < %s -aa-pipeline=basic-aa -passes=loop-vectorize,instcombine -S -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
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; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -S | FileCheck %s -check-prefix=FORCE
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK-LABEL: PR31671
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;
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; Check a pointer in which one of its uses is consecutive-like and another of
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; its uses is non-consecutive-like. In the test case below, %tmp3 is the
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; pointer operand of an interleaved load, making it consecutive-like. However,
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; it is also the pointer operand of a non-interleaved store that will become a
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; scatter operation. %tmp3 (and the induction variable) should not be marked
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; uniform-after-vectorization.
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;
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; CHECK: LV: Found uniform instruction: %tmp0 = getelementptr inbounds %data, ptr %d, i64 0, i32 3, i64 %i
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; CHECK-NOT: LV: Found uniform instruction: %tmp3 = getelementptr inbounds %data, ptr %d, i64 0, i32 0, i64 %i
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; CHECK-NOT: LV: Found uniform instruction: %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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; CHECK-NOT: LV: Found uniform instruction: %i.next = add nuw nsw i64 %i, 5
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%data = type { [32000 x float], [3 x i32], [4 x i8], [32000 x float] }
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define void @PR31671(float %x, ptr %d) #0 {
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; CHECK-LABEL: define void @PR31671(
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; CHECK-SAME: float [[X:%.*]], ptr [[D:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x float> poison, float [[X]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x float> [[BROADCAST_SPLATINSERT]], <16 x float> poison, <16 x i32> zeroinitializer
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ <i64 0, i64 5, i64 10, i64 15, i64 20, i64 25, i64 30, i64 35, i64 40, i64 45, i64 50, i64 55, i64 60, i64 65, i64 70, i64 75>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 5
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[DATA:%.*]], ptr [[D]], i64 0, i32 3, i64 [[OFFSET_IDX]]
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; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <80 x float>, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <80 x float> [[WIDE_VEC]], <80 x float> poison, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 35, i32 40, i32 45, i32 50, i32 55, i32 60, i32 65, i32 70, i32 75>
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; CHECK-NEXT: [[TMP1:%.*]] = fmul <16 x float> [[BROADCAST_SPLAT]], [[STRIDED_VEC]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, <16 x i64> [[VEC_IND]]
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <16 x ptr> [[TMP2]], i64 0
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; CHECK-NEXT: [[WIDE_VEC1:%.*]] = load <80 x float>, ptr [[TMP3]], align 4
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; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <80 x float> [[WIDE_VEC1]], <80 x float> poison, <16 x i32> <i32 0, i32 5, i32 10, i32 15, i32 20, i32 25, i32 30, i32 35, i32 40, i32 45, i32 50, i32 55, i32 60, i32 65, i32 70, i32 75>
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; CHECK-NEXT: [[TMP4:%.*]] = fadd <16 x float> [[STRIDED_VEC2]], [[TMP1]]
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; CHECK-NEXT: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> [[TMP4]], <16 x ptr> [[TMP2]], i32 4, <16 x i1> splat (i1 true))
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], splat (i64 80)
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 6384
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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;
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; FORCE-LABEL: define void @PR31671(
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; FORCE-SAME: float [[X:%.*]], ptr [[D:%.*]]) #[[ATTR0:[0-9]+]] {
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; FORCE-NEXT: [[ENTRY:.*:]]
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; FORCE-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; FORCE: [[VECTOR_PH]]:
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; FORCE-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x float> poison, float [[X]], i64 0
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; FORCE-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x float> [[BROADCAST_SPLATINSERT]], <2 x float> poison, <2 x i32> zeroinitializer
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; FORCE-NEXT: br label %[[VECTOR_BODY:.*]]
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; FORCE: [[VECTOR_BODY]]:
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; FORCE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; FORCE-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 5
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; FORCE-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
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; FORCE-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 5
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; FORCE-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 10
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; FORCE-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 15
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; FORCE-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 20
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; FORCE-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 25
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; FORCE-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 30
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; FORCE-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 35
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; FORCE-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[DATA:%.*]], ptr [[D]], i64 0, i32 3, i64 [[TMP0]]
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; FORCE-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 3, i64 [[TMP2]]
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; FORCE-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 3, i64 [[TMP4]]
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; FORCE-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 3, i64 [[TMP6]]
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; FORCE-NEXT: [[WIDE_VEC:%.*]] = load <10 x float>, ptr [[TMP8]], align 4
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; FORCE-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <10 x float> [[WIDE_VEC]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[WIDE_VEC1:%.*]] = load <10 x float>, ptr [[TMP9]], align 4
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; FORCE-NEXT: [[STRIDED_VEC2:%.*]] = shufflevector <10 x float> [[WIDE_VEC1]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[WIDE_VEC3:%.*]] = load <10 x float>, ptr [[TMP10]], align 4
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; FORCE-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <10 x float> [[WIDE_VEC3]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[WIDE_VEC5:%.*]] = load <10 x float>, ptr [[TMP11]], align 4
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; FORCE-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <10 x float> [[WIDE_VEC5]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[TMP12:%.*]] = fmul <2 x float> [[BROADCAST_SPLAT]], [[STRIDED_VEC]]
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; FORCE-NEXT: [[TMP13:%.*]] = fmul <2 x float> [[BROADCAST_SPLAT]], [[STRIDED_VEC2]]
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; FORCE-NEXT: [[TMP14:%.*]] = fmul <2 x float> [[BROADCAST_SPLAT]], [[STRIDED_VEC4]]
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; FORCE-NEXT: [[TMP15:%.*]] = fmul <2 x float> [[BROADCAST_SPLAT]], [[STRIDED_VEC6]]
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; FORCE-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP0]]
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; FORCE-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP1]]
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; FORCE-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP2]]
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; FORCE-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP3]]
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; FORCE-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP4]]
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; FORCE-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP5]]
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; FORCE-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP6]]
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; FORCE-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[DATA]], ptr [[D]], i64 0, i32 0, i64 [[TMP7]]
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; FORCE-NEXT: [[WIDE_VEC7:%.*]] = load <10 x float>, ptr [[TMP16]], align 4
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; FORCE-NEXT: [[STRIDED_VEC8:%.*]] = shufflevector <10 x float> [[WIDE_VEC7]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[WIDE_VEC9:%.*]] = load <10 x float>, ptr [[TMP18]], align 4
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; FORCE-NEXT: [[STRIDED_VEC10:%.*]] = shufflevector <10 x float> [[WIDE_VEC9]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[WIDE_VEC11:%.*]] = load <10 x float>, ptr [[TMP20]], align 4
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; FORCE-NEXT: [[STRIDED_VEC12:%.*]] = shufflevector <10 x float> [[WIDE_VEC11]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[WIDE_VEC13:%.*]] = load <10 x float>, ptr [[TMP22]], align 4
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; FORCE-NEXT: [[STRIDED_VEC14:%.*]] = shufflevector <10 x float> [[WIDE_VEC13]], <10 x float> poison, <2 x i32> <i32 0, i32 5>
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; FORCE-NEXT: [[TMP24:%.*]] = fadd <2 x float> [[STRIDED_VEC8]], [[TMP12]]
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; FORCE-NEXT: [[TMP25:%.*]] = fadd <2 x float> [[STRIDED_VEC10]], [[TMP13]]
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; FORCE-NEXT: [[TMP26:%.*]] = fadd <2 x float> [[STRIDED_VEC12]], [[TMP14]]
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; FORCE-NEXT: [[TMP27:%.*]] = fadd <2 x float> [[STRIDED_VEC14]], [[TMP15]]
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; FORCE-NEXT: [[TMP28:%.*]] = extractelement <2 x float> [[TMP24]], i32 0
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; FORCE-NEXT: store float [[TMP28]], ptr [[TMP16]], align 4
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; FORCE-NEXT: [[TMP29:%.*]] = extractelement <2 x float> [[TMP24]], i32 1
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; FORCE-NEXT: store float [[TMP29]], ptr [[TMP17]], align 4
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; FORCE-NEXT: [[TMP30:%.*]] = extractelement <2 x float> [[TMP25]], i32 0
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; FORCE-NEXT: store float [[TMP30]], ptr [[TMP18]], align 4
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; FORCE-NEXT: [[TMP31:%.*]] = extractelement <2 x float> [[TMP25]], i32 1
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; FORCE-NEXT: store float [[TMP31]], ptr [[TMP19]], align 4
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; FORCE-NEXT: [[TMP32:%.*]] = extractelement <2 x float> [[TMP26]], i32 0
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; FORCE-NEXT: store float [[TMP32]], ptr [[TMP20]], align 4
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; FORCE-NEXT: [[TMP33:%.*]] = extractelement <2 x float> [[TMP26]], i32 1
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; FORCE-NEXT: store float [[TMP33]], ptr [[TMP21]], align 4
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; FORCE-NEXT: [[TMP34:%.*]] = extractelement <2 x float> [[TMP27]], i32 0
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; FORCE-NEXT: store float [[TMP34]], ptr [[TMP22]], align 4
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; FORCE-NEXT: [[TMP35:%.*]] = extractelement <2 x float> [[TMP27]], i32 1
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; FORCE-NEXT: store float [[TMP35]], ptr [[TMP23]], align 4
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; FORCE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; FORCE-NEXT: [[TMP36:%.*]] = icmp eq i64 [[INDEX_NEXT]], 6392
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; FORCE-NEXT: br i1 [[TMP36]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; FORCE: [[MIDDLE_BLOCK]]:
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; FORCE-NEXT: br label %[[SCALAR_PH]]
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; FORCE: [[SCALAR_PH]]:
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;
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%tmp0 = getelementptr inbounds %data, ptr %d, i64 0, i32 3, i64 %i
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%tmp1 = load float, ptr %tmp0, align 4
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%tmp2 = fmul float %x, %tmp1
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%tmp3 = getelementptr inbounds %data, ptr %d, i64 0, i32 0, i64 %i
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%tmp4 = load float, ptr %tmp3, align 4
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%tmp5 = fadd float %tmp4, %tmp2
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store float %tmp5, ptr %tmp3, align 4
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%i.next = add nuw nsw i64 %i, 5
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%cond = icmp slt i64 %i.next, 32000
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br i1 %cond, label %for.body, label %for.end
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for.end:
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ret void
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}
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attributes #0 = { "target-cpu"="knl" }
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; CHECK-LABEL: PR40816
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;
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; Check that scalar with predication instructions are not considered uniform
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; after vectorization, because that results in replicating a region instead of
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; having a single instance (out of VF). The predication stems from a tiny count
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; of 3 leading to folding the tail by masking using icmp ule <i, i+1> <= <2, 2>.
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;
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; CHECK: LV: Found trip count: 3
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; CHECK: LV: Found uniform instruction: {{%.*}} = icmp eq i32 {{%.*}}, 0
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; CHECK-NOT: LV: Found uniform instruction: {{%.*}} = load i32, ptr {{%.*}}, align 1
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; CHECK: LV: Found not uniform due to requiring predication: {{%.*}} = load i32, ptr {{%.*}}, align 1
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; CHECK: LV: Found scalar instruction: {{%.*}} = getelementptr inbounds [3 x i32], ptr @a, i32 0, i32 {{%.*}}
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;
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;
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@a = internal constant [3 x i32] [i32 7, i32 7, i32 0], align 1
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@b = external global i32, align 1
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define void @PR40816() #1 {
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; CHECK-LABEL: define void @PR40816(
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; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[FOR_BODY:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[INC:%.*]], %[[FOR_BODY]] ]
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; CHECK-NEXT: store i32 [[TMP0]], ptr @b, align 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[TMP0]], 2
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[TMP0]], 1
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; CHECK-NEXT: br i1 [[CMP2]], label %[[RETURN:.*]], label %[[FOR_BODY]]
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; CHECK: [[RETURN]]:
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; CHECK-NEXT: ret void
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;
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; FORCE-LABEL: define void @PR40816(
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; FORCE-SAME: ) #[[ATTR1:[0-9]+]] {
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; FORCE-NEXT: [[ENTRY:.*:]]
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; FORCE-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; FORCE: [[VECTOR_PH]]:
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; FORCE-NEXT: br label %[[VECTOR_BODY:.*]]
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; FORCE: [[VECTOR_BODY]]:
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; FORCE-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
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; FORCE-NEXT: [[VEC_IND:%.*]] = phi <2 x i8> [ <i8 0, i8 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE4]] ]
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; FORCE-NEXT: [[TMP2:%.*]] = icmp ule <2 x i8> [[VEC_IND]], splat (i8 2)
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; FORCE-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
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; FORCE-NEXT: br i1 [[TMP3]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
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; FORCE: [[PRED_STORE_IF]]:
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; FORCE-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
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; FORCE-NEXT: store i32 [[TMP0]], ptr @b, align 1
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; FORCE-NEXT: br label %[[PRED_STORE_CONTINUE]]
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; FORCE: [[PRED_STORE_CONTINUE]]:
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; FORCE-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
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; FORCE-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE4]]
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; FORCE: [[PRED_STORE_IF1]]:
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; FORCE-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 1
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; FORCE-NEXT: store i32 [[TMP1]], ptr @b, align 1
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; FORCE-NEXT: br label %[[PRED_STORE_CONTINUE4]]
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; FORCE: [[PRED_STORE_CONTINUE4]]:
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; FORCE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; FORCE-NEXT: [[VEC_IND_NEXT]] = add <2 x i8> [[VEC_IND]], splat (i8 2)
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; FORCE-NEXT: [[TMP15:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
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; FORCE-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; FORCE: [[MIDDLE_BLOCK]]:
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; FORCE-NEXT: br [[RETURN:label %.*]]
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; FORCE: [[SCALAR_PH]]:
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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store i32 %0, ptr @b, align 1
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%arrayidx1 = getelementptr inbounds [3 x i32], ptr @a, i32 0, i32 %0
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%1 = load i32, ptr %arrayidx1, align 1
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%cmp2 = icmp eq i32 %1, 0
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%inc = add nuw nsw i32 %0, 1
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br i1 %cmp2, label %return, label %for.body
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return: ; preds = %for.body
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ret void
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}
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attributes #1 = { "target-cpu"="core2" }
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