043b04acff
This reverts commit 8dd160f4767f971572eac065c8650d9202ff5bf9. The recommit contains an adjustment to planContainsAdditionalSimplifications, which considers changes to the original predicate for compares. Original commit message: Add simplification to fold negation into a compare, if the negation is the only user of the compare. This removes a number of redundant negations. Alive2 Proofs for FPCMP test changes: https://alive2.llvm.org/ce/z/WGDz9U PR: https://github.com/llvm/llvm-project/pull/129430
63 lines
2.2 KiB
LLVM
63 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-vectorize -S %s | FileCheck %s
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target triple = "i386-unknow-linux"
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define void @icmp_predicate_and_branch_cost(i32 %size, ptr %dst, i64 %conv5.i) #0 {
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; CHECK-LABEL: @icmp_predicate_and_branch_cost(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
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; CHECK-NEXT: [[EXT_IV:%.*]] = zext i32 [[IV]] to i64
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; CHECK-NEXT: [[ADD_IV:%.*]] = add i64 [[EXT_IV]], 8
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; CHECK-NEXT: [[C_1:%.*]] = icmp ugt i64 [[ADD_IV]], [[CONV5_I:%.*]]
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; CHECK-NEXT: br i1 [[C_1]], label [[THEN_1:%.*]], label [[LOOP_LATCH]]
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; CHECK: then.1:
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; CHECK-NEXT: [[C_2:%.*]] = icmp ult i32 [[IV]], [[SIZE:%.*]]
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; CHECK-NEXT: br i1 [[C_2]], label [[THEN_2:%.*]], label [[LOOP_LATCH]]
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; CHECK: then.2:
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; CHECK-NEXT: [[OR:%.*]] = or i32 [[SIZE]], [[IV]]
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; CHECK-NEXT: [[TRUNC_OR:%.*]] = trunc i32 [[OR]] to i8
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop.latch:
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; CHECK-NEXT: [[SINK:%.*]] = phi i8 [ [[TRUNC_OR]], [[THEN_2]] ], [ 1, [[LOOP_HEADER]] ], [ 0, [[THEN_1]] ]
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; CHECK-NEXT: store i8 [[SINK]], ptr [[DST:%.*]], align 1
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; CHECK-NEXT: [[IV_NEXT]] = trunc i64 [[ADD_IV]] to i32
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; CHECK-NEXT: [[C_3:%.*]] = icmp ugt i32 [[SIZE]], [[IV]]
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; CHECK-NEXT: br i1 [[C_3]], label [[LOOP_HEADER]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%ext.iv = zext i32 %iv to i64
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%add.iv = add i64 %ext.iv, 8
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%c.1 = icmp ugt i64 %add.iv, %conv5.i
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br i1 %c.1, label %then.1, label %loop.latch
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then.1:
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%c.2 = icmp ult i32 %iv, %size
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br i1 %c.2, label %then.2, label %loop.latch
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then.2:
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%or = or i32 %size, %iv
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%trunc.or = trunc i32 %or to i8
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br label %loop.latch
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loop.latch:
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%sink = phi i8 [ %trunc.or, %then.2 ], [ 1, %loop.header ], [ 0, %then.1 ]
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store i8 %sink, ptr %dst, align 1
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%iv.next = trunc i64 %add.iv to i32
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%c.3 = icmp ugt i32 %size, %iv
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br i1 %c.3, label %loop.header, label %exit
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exit:
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ret void
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}
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attributes #0 = { mustprogress "target-cpu"="pentium4" }
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