db98ac43ec
Directly emit shl instead of a multiply if VF * Step is a power-of-2. The main motivation here is to prepare the code and test for directly generating and expanding a SCEV expression of the minimum iteration count. SCEVExpander will directly emit shl for multiplies with powers-of-2. InstCombine will also performs this combine, so end-to-end this should effectively by NFC. PR: https://github.com/llvm/llvm-project/pull/153495
87 lines
5.1 KiB
LLVM
87 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -scalable-vectorization=on -force-target-supports-scalable-vectors=true -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=2 -S %s | FileCheck %s
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define i32 @iv_live_out_wide(ptr %dst) {
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; CHECK-LABEL: define i32 @iv_live_out_wide(
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; CHECK-SAME: ptr [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[STEP_1:%.*]] = sext i8 0 to i32
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; CHECK-NEXT: [[STEP_2:%.*]] = add nsw i32 [[STEP_1]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 [[TMP0]], 2
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 2000, [[TMP1]]
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP4]], 2
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[TMP5]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], 2
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 2000, [[TMP6]]
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 2000, [[N_MOD_VF]]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i32> poison, i32 [[STEP_2]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i32> @llvm.stepvector.nxv2i32()
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; CHECK-NEXT: [[TMP8:%.*]] = mul <vscale x 2 x i32> [[TMP7]], splat (i32 1)
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i32> zeroinitializer, [[TMP8]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[STEP_ADD:%.*]] = add <vscale x 2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[INDEX]]
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; CHECK-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP13:%.*]] = shl nuw i64 [[TMP12]], 1
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i16, ptr [[TMP10]], i64 [[TMP13]]
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; CHECK-NEXT: store <vscale x 2 x i16> zeroinitializer, ptr [[TMP10]], align 2
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; CHECK-NEXT: store <vscale x 2 x i16> zeroinitializer, ptr [[TMP14]], align 2
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; CHECK-NEXT: [[TMP15:%.*]] = add <vscale x 2 x i32> [[BROADCAST_SPLAT]], [[STEP_ADD]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP6]]
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i32> [[STEP_ADD]], [[BROADCAST_SPLAT2]]
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; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 2
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; CHECK-NEXT: [[TMP19:%.*]] = sub i32 [[TMP18]], 1
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; CHECK-NEXT: [[TMP20:%.*]] = extractelement <vscale x 2 x i32> [[TMP15]], i32 [[TMP19]]
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 2000, [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[E_EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[IV]]
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; CHECK-NEXT: store i16 0, ptr [[GEP_DST]], align 2
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[STEP_2]], [[IV]]
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i32 [[IV_NEXT]], 2000
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; CHECK-NEXT: br i1 [[CMP_I]], label %[[LOOP]], label %[[E_EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[E_EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[IV_NEXT]], %[[LOOP]] ], [ [[TMP20]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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entry:
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%step.1 = sext i8 0 to i32
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%step.2 = add nsw i32 %step.1, 1
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%gep.dst = getelementptr inbounds i16, ptr %dst, i32 %iv
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store i16 0, ptr %gep.dst, align 2
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%iv.next = add i32 %step.2, %iv
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%cmp.i = icmp slt i32 %iv.next, 2000
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br i1 %cmp.i, label %loop, label %e.exit
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e.exit:
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%res = phi i32 [ %iv.next, %loop ]
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ret i32 %res
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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;.
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