d88389aa7e
Summary: Sandy Bridge and later CPUs have better throughput using a SHLD to implement rotate versus the normal rotate instructions. Additionally it saves one uop and avoids a partial flag update dependency. This patch implements this change on any Sandy Bridge or later processor without BMI2 instructions. With BMI2 we will use RORX as we currently do. Reviewers: zvi Reviewed By: zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30181 llvm-svn: 295697
126 lines
2.4 KiB
LLVM
126 lines
2.4 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
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; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s --check-prefix=SHLD
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; RUN: llc < %s -march=x86 -mcpu=core-avx2 | FileCheck %s --check-prefix=BMI2
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define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: foo:
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; CHECK: roll %cl
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%0 = shl i32 %x, %z
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%1 = sub i32 32, %z
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%2 = lshr i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: bar:
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; CHECK: shldl %cl
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%0 = shl i32 %y, %z
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%1 = sub i32 32, %z
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%2 = lshr i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: un:
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; CHECK: rorl %cl
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%0 = lshr i32 %x, %z
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%1 = sub i32 32, %z
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%2 = shl i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: bu:
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; CHECK: shrdl %cl
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%0 = lshr i32 %y, %z
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%1 = sub i32 32, %z
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%2 = shl i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: xfoo:
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; CHECK: roll $7
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; SHLD-LABEL: xfoo:
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; SHLD: shldl $7
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; BMI2-LABEL: xfoo:
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; BMI2: rorxl $25
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%0 = lshr i32 %x, 25
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%1 = shl i32 %x, 7
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%2 = or i32 %0, %1
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ret i32 %2
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}
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define i32 @xfoop(i32* %p) nounwind readnone {
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entry:
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; CHECK-LABEL: xfoop:
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; CHECK: roll $7
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; SHLD-LABEL: xfoop:
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; SHLD: shldl $7
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; BMI2-LABEL: xfoop:
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; BMI2: rorxl $25
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%x = load i32, i32* %p
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%a = lshr i32 %x, 25
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%b = shl i32 %x, 7
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%c = or i32 %a, %b
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ret i32 %c
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}
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define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: xbar:
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; CHECK: shldl $7
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%0 = shl i32 %y, 7
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%1 = lshr i32 %x, 25
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%2 = or i32 %0, %1
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ret i32 %2
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}
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define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: xun:
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; CHECK: roll $25
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; SHLD-LABEL: xun:
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; SHLD: shldl $25
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; BMI2-LABEL: xun:
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; BMI2: rorxl $7
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%0 = lshr i32 %x, 7
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%1 = shl i32 %x, 25
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%2 = or i32 %0, %1
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ret i32 %2
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}
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define i32 @xunp(i32* %p) nounwind readnone {
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entry:
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; CHECK-LABEL: xunp:
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; CHECK: roll $25
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; shld-label: xunp:
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; shld: shldl $25
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; BMI2-LABEL: xunp:
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; BMI2: rorxl $7
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%x = load i32, i32* %p
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%a = lshr i32 %x, 7
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%b = shl i32 %x, 25
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%c = or i32 %a, %b
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ret i32 %c
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}
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define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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; CHECK-LABEL: xbu:
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; CHECK: shldl $25
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%0 = lshr i32 %y, 7
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%1 = shl i32 %x, 25
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%2 = or i32 %0, %1
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ret i32 %2
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}
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