6dbc01e801
This is a NFC patch. This patch run a bulk update on CodeGen tests that are impacted by the true16 features. This patch applies: 1. duplicate GFX11plus runlines and apply them with "+mattr=+real-true16" and "+mattr=-real-true16" 2. update the test with the update script For some GISEL runlines, the current CodeGen do not fully support the true16 version. Still update the runlines, but comment out the failing one, and added a "FIXME-TRUE16" comment to that test for easier tracking. These test will be fixed in the following patches. This is in a transition state that we support both "+real-true16/-real-true16" in our code base. We plan to move to "+real-true16" as default, and finally remove "-real-true16" mode and test lines.
394 lines
13 KiB
LLVM
394 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
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; Make sure stack use isn't introduced for these bitcasts.
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define i160 @bitcast_v5i32_to_i160(<5 x i32> %vec) {
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; GFX9-LABEL: bitcast_v5i32_to_i160:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_v5i32_to_i160:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <5 x i32> %vec to i160
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ret i160 %bitcast
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}
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define i192 @bitcast_v6i32_to_i192(<6 x i32> %vec) {
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; GFX9-LABEL: bitcast_v6i32_to_i192:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_v6i32_to_i192:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <6 x i32> %vec to i192
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ret i192 %bitcast
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}
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define i224 @bitcast_v7i32_to_i224(<7 x i32> %vec) {
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; GFX9-LABEL: bitcast_v7i32_to_i224:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_v7i32_to_i224:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <7 x i32> %vec to i224
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ret i224 %bitcast
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}
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define i256 @bitcast_v8i32_to_i256(<8 x i32> %vec) {
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; GFX9-LABEL: bitcast_v8i32_to_i256:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_v8i32_to_i256:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <8 x i32> %vec to i256
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ret i256 %bitcast
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}
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define <5 x i32> @bitcast_i160_to_v5i32(i160 %int) {
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; GFX9-LABEL: bitcast_i160_to_v5i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_i160_to_v5i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i160 %int to <5 x i32>
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ret <5 x i32> %bitcast
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}
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define <6 x i32> @bitcast_i192_to_v6i32(i192 %int) {
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; GFX9-LABEL: bitcast_i192_to_v6i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_i192_to_v6i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i192 %int to <6 x i32>
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ret <6 x i32> %bitcast
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}
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define <7 x i32> @bitcast_i224_to_v7i32(i224 %int) {
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; GFX9-LABEL: bitcast_i224_to_v7i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_i224_to_v7i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i224 %int to <7 x i32>
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ret <7 x i32> %bitcast
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}
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define <8 x i32> @bitcast_i256_to_v8i32(i256 %int) {
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; GFX9-LABEL: bitcast_i256_to_v8i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_i256_to_v8i32:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i256 %int to <8 x i32>
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ret <8 x i32> %bitcast
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}
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define i192 @bitcast_v3i64_to_i192(<3 x i64> %vec) {
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; GFX9-LABEL: bitcast_v3i64_to_i192:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_v3i64_to_i192:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <3 x i64> %vec to i192
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ret i192 %bitcast
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}
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define <3 x i64> @bitcast_i192_to_v3i64(i192 %int) {
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; GFX9-LABEL: bitcast_i192_to_v3i64:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_i192_to_v3i64:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i192 %int to <3 x i64>
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ret <3 x i64> %bitcast
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}
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define <10 x i16> @bitcast_i160_to_v10i16(i160 %int) {
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; GFX9-LABEL: bitcast_i160_to_v10i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_mov_b32 s4, 0xffff
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; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
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; GFX9-NEXT: v_bfi_b32 v2, s4, v2, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: bitcast_i160_to_v10i16:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
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; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX12-TRUE16-NEXT: v_bfi_b32 v0, 0xffff, v5, v0
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; GFX12-TRUE16-NEXT: v_bfi_b32 v2, 0xffff, v6, v2
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-FAKE16-LABEL: bitcast_i160_to_v10i16:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
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; GFX12-FAKE16-NEXT: v_bfi_b32 v2, 0xffff, v2, v2
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; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i160 %int to <10 x i16>
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ret <10 x i16> %bitcast
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}
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define i160 @bitcast_v10i16_to_i160(<10 x i16> %vec) {
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; GFX9-LABEL: bitcast_v10i16_to_i160:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: bitcast_v10i16_to_i160:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <10 x i16> %vec to i160
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ret i160 %bitcast
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}
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define i12 @bitcast_v2i6_to_i12(<2 x i6> %vec) {
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; GFX9-LABEL: bitcast_v2i6_to_i12:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshlrev_b16_e32 v1, 6, v1
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; GFX9-NEXT: v_and_b32_e32 v0, 63, v0
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; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
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; GFX9-NEXT: v_and_b32_e32 v0, 0xfff, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: bitcast_v2i6_to_i12:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 6, v1.l
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; GFX12-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 63
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v0.h
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; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xfff, v0.l
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-FAKE16-LABEL: bitcast_v2i6_to_i12:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-FAKE16-NEXT: v_lshlrev_b16 v1, 6, v1
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; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 63, v0
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; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
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; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xfff, v0
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; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast <2 x i6> %vec to i12
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ret i12 %bitcast
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}
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define <2 x i6> @bitcast_i12_to_v2i6(i12 %int) {
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; GFX9-LABEL: bitcast_i12_to_v2i6:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v2, 63, v0
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; GFX9-NEXT: v_lshrrev_b16_e32 v0, 6, v0
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; GFX9-NEXT: v_and_b32_e32 v1, 63, v0
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; GFX9-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: bitcast_i12_to_v2i6:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.h, 6, v0.l
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; GFX12-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 63
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-TRUE16-NEXT: v_and_b16 v1.l, v0.h, 63
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-FAKE16-LABEL: bitcast_i12_to_v2i6:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-FAKE16-NEXT: v_lshrrev_b16 v1, 6, v0
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; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 63, v0
|
|
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 63, v1
|
|
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%bitcast = bitcast i12 %int to <2 x i6>
|
|
ret <2 x i6> %bitcast
|
|
}
|
|
|
|
define i160 @bitcast_v5f32_to_i160(<5 x float> %vec) {
|
|
; GFX9-LABEL: bitcast_v5f32_to_i160:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX12-LABEL: bitcast_v5f32_to_i160:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%bitcast = bitcast <5 x float> %vec to i160
|
|
ret i160 %bitcast
|
|
}
|
|
|
|
define <5 x float> @bitcast_i160_to_v5f32(i160 %int) {
|
|
; GFX9-LABEL: bitcast_i160_to_v5f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX12-LABEL: bitcast_i160_to_v5f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%bitcast = bitcast i160 %int to <5 x float>
|
|
ret <5 x float> %bitcast
|
|
}
|
|
|
|
define <6 x float> @bitcast_i192_to_v6f32(i192 %int) {
|
|
; GFX9-LABEL: bitcast_i192_to_v6f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX12-LABEL: bitcast_i192_to_v6f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%bitcast = bitcast i192 %int to <6 x float>
|
|
ret <6 x float> %bitcast
|
|
}
|
|
|
|
define i192 @bitcast_v6f32_to_i192(<6 x float> %vec) {
|
|
; GFX9-LABEL: bitcast_v6f32_to_i192:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX12-LABEL: bitcast_v6f32_to_i192:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
|
; GFX12-NEXT: s_wait_expcnt 0x0
|
|
; GFX12-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
|
%bitcast = bitcast <6 x float> %vec to i192
|
|
ret i192 %bitcast
|
|
}
|