9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
189 lines
6.6 KiB
LLVM
189 lines
6.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_default_si:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_default_si(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #0 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_default_vi:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_default_vi(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #1 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f64_denormals:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #2 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f32_denormals:
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; GCNL: FloatMode: 48
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #3 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f32_f64_denormals:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f32_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #4 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_no_denormals
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; GCN: FloatMode: 0
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_no_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #5 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f16_f64_denormals:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f16_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #6 {
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store half 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_no_f16_f64_denormals:
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; GCN: FloatMode: 48
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_no_f16_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #7 {
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store half 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f32_f16_f64_denormals:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f32_f16_f64_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %out2) #8 {
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store half 0.0, ptr addrspace(1) %out0
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store float 0.0, ptr addrspace(1) %out1
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store double 0.0, ptr addrspace(1) %out2
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ret void
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}
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; GCN-LABEL: {{^}}test_just_f32_attr_flush
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; GCN: FloatMode: 192
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_just_f32_attr_flush(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #9 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_flush_all_outputs:
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; GCN: FloatMode: 80
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_flush_all_outputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #10 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_flush_all_inputs:
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; GCN: FloatMode: 160
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_flush_all_inputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #11 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_flush_f32_inputs:
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; GCN: FloatMode: 224
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_flush_f32_inputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #12 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_flush_f32_outputs:
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; GCN: FloatMode: 208
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_flush_f32_outputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #13 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_flush_f64_inputs:
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; GCN: FloatMode: 176
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_flush_f64_inputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #14 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_flush_f64_outputs:
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; GCN: FloatMode: 112
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_flush_f64_outputs(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #15 {
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store float 0.0, ptr addrspace(1) %out0
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store double 0.0, ptr addrspace(1) %out1
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ret void
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}
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; GCN-LABEL: {{^}}kill_gs_const:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 0
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define amdgpu_gs void @kill_gs_const() {
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main_body:
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%cmp0 = icmp ule i32 0, 3
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call void @llvm.amdgcn.kill(i1 %cmp0)
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%cmp1 = icmp ule i32 3, 0
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call void @llvm.amdgcn.kill(i1 %cmp1)
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ret void
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}
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; GCN-LABEL: {{^}}kill_vcc_implicit_def:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 0
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define amdgpu_ps float @kill_vcc_implicit_def(ptr addrspace(4) inreg, ptr addrspace(4) inreg, ptr addrspace(4) inreg, ptr addrspace(4) inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
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entry:
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%tmp0 = fcmp olt float %13, 0.0
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call void @llvm.amdgcn.kill(i1 %tmp0)
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%tmp1 = select i1 %tmp0, float 1.0, float 0.0
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ret float %tmp1
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}
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declare void @llvm.amdgcn.kill(i1)
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attributes #0 = { nounwind "target-cpu"="tahiti" }
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attributes #1 = { nounwind "target-cpu"="fiji" }
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attributes #2 = { nounwind "denormal-fp-math"="ieee,ieee" }
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attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }
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attributes #4 = { nounwind "denormal-fp-math"="ieee,ieee" }
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attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }
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attributes #6 = { nounwind "denormal-fp-math"="ieee,ieee" }
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attributes #7 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" }
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attributes #8 = { nounwind "denormal-fp-math"="ieee,ieee" }
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attributes #9 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
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attributes #10 = { nounwind "denormal-fp-math"="preserve-sign,ieee" }
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attributes #11 = { nounwind "denormal-fp-math"="ieee,preserve-sign" }
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attributes #12 = { nounwind "denormal-fp-math-f32"="ieee,preserve-sign" "denormal-fp-math"="ieee,ieee" }
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attributes #13 = { nounwind "denormal-fp-math-f32"="preserve-sign,ieee" "denormal-fp-math"="ieee,ieee" }
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attributes #14 = { nounwind "denormal-fp-math"="ieee,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" }
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attributes #15 = { nounwind "denormal-fp-math"="preserve-sign,ieee" "denormal-fp-math-f32"="ieee,ieee" }
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