8cc6c2e80f
andorbitset.ll is interesting since it directly depends on the difference between poison and undef. Not sure it's useful to keep the version using poison, I assume none of this code makes it to codegen. si-spill-cf.ll was also a nasty case, which I doubt has been reproducing its original issue for a very long time. I had to reclaim an older version, replace some of the poison uses, and run simplify-cfg. There's a very slight change in the final CFG with this, but final the output is approximately the same as it used to be.
234 lines
8.7 KiB
LLVM
234 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs -disable-machine-sink=1 - < %s | FileCheck -check-prefix=GFX10 %s
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define float @fold_abs_in_branch(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_abs_in_branch:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: s_mov_b32 s4, exec_lo
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; GFX10-NEXT: v_add_f32_e32 v1, v0, v1
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; GFX10-NEXT: v_add_f32_e64 v0, |v1|, |v1|
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; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0
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; GFX10-NEXT: ; %bb.1: ; %if
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; GFX10-NEXT: v_mul_f32_e64 v0, 0x3e4ccccd, |v1|
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
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%3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%4 = fcmp ule float %3, 1.000000e+00
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br i1 %4, label %if, label %exit
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if:
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%if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
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br label %exit
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exit:
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%ret = phi float [ %3, %entry ], [ %if.3, %if ]
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ret float %ret
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}
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define float @fold_abs_in_branch_multiple_users(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_abs_in_branch_multiple_users:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: s_mov_b32 s4, exec_lo
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: v_add_f32_e64 v1, |v0|, |v0|
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; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v1
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; GFX10-NEXT: ; %bb.1: ; %if
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; GFX10-NEXT: v_mul_f32_e64 v1, 0x3e4ccccd, |v0|
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: v_add_f32_e64 v0, |v0|, 2.0
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; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
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%3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%4 = fcmp ule float %3, 1.000000e+00
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br i1 %4, label %if, label %exit
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if:
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%if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
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br label %exit
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exit:
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%exit.phi = phi float [ %3, %entry ], [ %if.3, %if ]
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%ret.0 = fadd reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%ret.1 = fmul float %ret.0, %exit.phi
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ret float %ret.1
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}
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define float @fold_abs_in_branch_undef(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_abs_in_branch_undef:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_add_f32_e64 v0, |s4|, |s4|
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; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, 1.0, v0
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; GFX10-NEXT: s_cbranch_vccnz .LBB2_2
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; GFX10-NEXT: ; %bb.1: ; %if
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; GFX10-NEXT: v_mul_f32_e64 v0, 0x3e4ccccd, |s4|
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; GFX10-NEXT: .LBB2_2: ; %exit
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%undef = freeze float poison
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%2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %undef)
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%3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%4 = fcmp ule float %3, 1.000000e+00
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br i1 %4, label %if, label %exit
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if:
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%if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
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br label %exit
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exit:
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%ret = phi float [ %3, %entry ], [ %if.3, %if ]
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ret float %ret
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}
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define float @fold_abs_in_branch_poison(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_abs_in_branch_poison:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float poison)
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%3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%4 = fcmp ule float %3, 1.000000e+00
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br i1 %4, label %if, label %exit
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if:
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%if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
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br label %exit
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exit:
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%ret = phi float [ %3, %entry ], [ %if.3, %if ]
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ret float %ret
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}
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define float @fold_abs_in_branch_fabs(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_abs_in_branch_fabs:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: s_mov_b32 s4, exec_lo
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; GFX10-NEXT: v_add_f32_e32 v1, v0, v1
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; GFX10-NEXT: v_add_f32_e64 v0, |v1|, |v1|
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; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0
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; GFX10-NEXT: ; %bb.1: ; %if
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; GFX10-NEXT: v_mul_f32_e64 v0, 0x3e4ccccd, |v1|
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
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%3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%4 = fcmp ule float %3, 1.000000e+00
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br i1 %4, label %if, label %exit
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if:
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%if.fabs = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %2)
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%if.3 = fmul reassoc nnan nsz arcp contract afn float %if.fabs, 0x3FC99999A0000000
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br label %exit
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exit:
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%ret = phi float [ %3, %entry ], [ %if.3, %if ]
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ret float %ret
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}
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define float @fold_abs_in_branch_phi(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_abs_in_branch_phi:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: s_mov_b32 s4, exec_lo
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: v_add_f32_e64 v0, |v0|, |v0|
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; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0
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; GFX10-NEXT: s_cbranch_execz .LBB5_3
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; GFX10-NEXT: ; %bb.1: ; %header.preheader
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; GFX10-NEXT: ; implicit-def: $vgpr0
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; GFX10-NEXT: .LBB5_2: ; %header
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: v_mul_f32_e32 v0, 0x40400000, v0
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; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, -1.0, v0
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; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
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; GFX10-NEXT: s_cbranch_vccnz .LBB5_2
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; GFX10-NEXT: .LBB5_3: ; %Flow1
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
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%3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
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%4 = fcmp ule float %3, 1.000000e+00
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br i1 %4, label %header, label %exit
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header:
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%h.fabs.phi = phi float [ poison, %entry ], [ %l.fabs, %l ]
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%h.fmul = fmul reassoc nnan nsz arcp contract afn float %h.fabs.phi, 2.000000e+00
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%l.1 = fmul reassoc nnan nsz arcp contract afn float %h.fabs.phi, 3.000000e+00
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br label %l
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l:
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%l.e = fcmp ule float %l.1, -1.000000e+00
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%l.fabs = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %l.1)
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br i1 %l.e, label %exit, label %header
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exit:
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%ret = phi float [ %3, %entry ], [ %l.fabs, %l ]
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ret float %ret
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}
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define float @fold_neg_in_branch(float %arg1, float %arg2) {
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; GFX10-LABEL: fold_neg_in_branch:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: s_mov_b32 s4, exec_lo
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; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
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; GFX10-NEXT: v_mov_b32_e32 v1, v0
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; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0
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; GFX10-NEXT: ; %bb.1: ; %if
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; GFX10-NEXT: v_rcp_f32_e64 v1, -v0
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; GFX10-NEXT: v_mul_f32_e64 v1, |v0|, v1
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX10-NEXT: v_mul_f32_e64 v0, -v0, v1
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
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%1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
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%2 = fneg reassoc nnan nsz arcp contract afn float %1
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%3 = fcmp ule float %1, 1.000000e+00
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br i1 %3, label %if, label %exit
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if:
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%if.fabs = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
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%if.3 = fdiv reassoc nnan nsz arcp contract afn float %if.fabs, %2
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br label %exit
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exit:
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%ret = phi float [ %1, %entry ], [ %if.3, %if ]
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%ret.2 = fmul reassoc nnan nsz arcp contract afn float %2, %ret
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ret float %ret.2
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}
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declare float @llvm.fabs.f32(float)
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declare float @llvm.fmuladd.f32(float, float, float) #0
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