9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
77 lines
2.8 KiB
LLVM
77 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare double @llvm.fabs.f64(double) #1
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; FUNC-LABEL: @fp_to_sint_f64_i32
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; SI: v_cvt_i32_f64_e32
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define amdgpu_kernel void @fp_to_sint_f64_i32(ptr addrspace(1) %out, double %in) {
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%result = fptosi double %in to i32
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: @fp_to_sint_v2f64_v2i32
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; SI: v_cvt_i32_f64_e32
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; SI: v_cvt_i32_f64_e32
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define amdgpu_kernel void @fp_to_sint_v2f64_v2i32(ptr addrspace(1) %out, <2 x double> %in) {
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%result = fptosi <2 x double> %in to <2 x i32>
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store <2 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: @fp_to_sint_v4f64_v4i32
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; SI: v_cvt_i32_f64_e32
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; SI: v_cvt_i32_f64_e32
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; SI: v_cvt_i32_f64_e32
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; SI: v_cvt_i32_f64_e32
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define amdgpu_kernel void @fp_to_sint_v4f64_v4i32(ptr addrspace(1) %out, <4 x double> %in) {
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%result = fptosi <4 x double> %in to <4 x i32>
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store <4 x i32> %result, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: @fp_to_sint_i64_f64
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; CI-DAG: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
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; CI-DAG: v_trunc_f64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]]
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; CI-DAG: s_movk_i32 [[K0_EXP:s[0-9]+]], 0xffe0
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; CI-DAG: v_ldexp_f64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], [[K0_EXP]]
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; CI-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]]
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; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
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; CI-DAG: v_fma_f64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]], [[TRUNC]]
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; CI-DAG: v_cvt_u32_f64_e32 v[[LO:[0-9]+]], [[FMA]]
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; CI-DAG: v_cvt_i32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]]
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; CI: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
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define amdgpu_kernel void @fp_to_sint_i64_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep = getelementptr double, ptr addrspace(1) %in, i32 %tid
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%val = load double, ptr addrspace(1) %gep, align 8
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%cast = fptosi double %val to i64
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store i64 %cast, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_f64_to_i1:
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; SI: v_cmp_eq_f64_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fp_to_sint_f64_to_i1(ptr addrspace(1) %out, double %in) #0 {
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%conv = fptosi double %in to i1
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store i1 %conv, ptr addrspace(1) %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_fabs_f64_to_i1:
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; SI: v_cmp_eq_f64_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, |s{{\[[0-9]+:[0-9]+\]}}|
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define amdgpu_kernel void @fp_to_sint_fabs_f64_to_i1(ptr addrspace(1) %out, double %in) #0 {
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%in.fabs = call double @llvm.fabs.f64(double %in)
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%conv = fptosi double %in.fabs to i1
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store i1 %conv, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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