2f8d699845
This is consistent with what's done on GISel. This allows the register coalescer to remove the redundant intermediate `s_mov_b32` instructions by using `m0` directly as the result register.
112 lines
5.3 KiB
LLVM
112 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN
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declare void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) nocapture, i32 %size, i32 %vindex, i32 %voffset, i32 %soffset, i32 %offset, i32 %aux)
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define amdgpu_ps float @buffer_load_lds_dword(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
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; GCN-LABEL: buffer_load_lds_dword:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: v_mov_b32_e32 v0, 8
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; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 idxen lds
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; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:4 glc lds
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; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:8 slc lds
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: ds_read_b32 v0, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: ; return to shader part epilog
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 0, i32 0)
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 4, i32 1)
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 8, i32 2)
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%res = load float, ptr addrspace(3) %lds
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ret float %res
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}
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define amdgpu_ps void @buffer_load_lds_dword_imm_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
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; GCN-LABEL: buffer_load_lds_dword_imm_offset:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:2048 lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 0, i32 0, i32 2048, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_load_lds_dword_v_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset) {
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; GCN-LABEL: buffer_load_lds_dword_v_offset:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], 0 idxen offen lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_load_lds_dword_s_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 inreg %soffset) {
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; GCN-LABEL: buffer_load_lds_dword_s_offset:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_dword v0, s[0:3], s5 idxen lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 0, i32 %soffset, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_load_lds_dword_vs_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GCN-LABEL: buffer_load_lds_dword_vs_offset:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], s5 idxen offen lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 %soffset, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_load_lds_dword_vs_imm_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GCN-LABEL: buffer_load_lds_dword_vs_imm_offset:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], s5 idxen offen offset:2048 lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 %soffset, i32 2048, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_load_lds_ushort(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
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; GCN-LABEL: buffer_load_lds_ushort:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: v_mov_b32_e32 v1, 0x800
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_ushort v[0:1], s[0:3], 0 idxen offen lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 2, i32 %vindex, i32 2048, i32 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @buffer_load_lds_ubyte(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
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; GCN-LABEL: buffer_load_lds_ubyte:
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; GCN: ; %bb.0: ; %main_body
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; GCN-NEXT: s_mov_b32 m0, s4
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: buffer_load_ubyte v0, s[0:3], 0 idxen offset:2048 lds
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; GCN-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.struct.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 1, i32 %vindex, i32 0, i32 0, i32 2048, i32 0)
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ret void
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}
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