9293b65a61
This is the next attempt to upstream this: https://github.com/llvm/llvm-project/pull/144947 The las one caused build errors in AArch64. Issue was resolved.
59 lines
2.7 KiB
LLVM
59 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GFX11
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX12
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define amdgpu_cs void @test_uniform_load_b96(ptr addrspace(1) %ptr, i32 %arg) "amdgpu-flat-work-group-size"="1,1" {
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; GFX11-LABEL: test_uniform_load_b96:
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; GFX11: ; %bb.0: ; %bb
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; GFX11-NEXT: v_mov_b32_e32 v3, 0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]
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; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo
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; GFX11-NEXT: v_readfirstlane_b32 s0, v2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: v_readfirstlane_b32 s1, v3
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x8
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_or_b32 s1, s2, s3
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_or_b32 s0, s0, s1
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; GFX11-NEXT: v_mov_b32_e32 v2, s0
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; GFX11-NEXT: global_store_b32 v[0:1], v2, off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: test_uniform_load_b96:
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; GFX12: ; %bb.0: ; %bb
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; GFX12-NEXT: v_mov_b32_e32 v3, 0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]
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; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo
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; GFX12-NEXT: v_readfirstlane_b32 s0, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: v_readfirstlane_b32 s1, v3
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; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_or_b32 s0, s0, s1
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; GFX12-NEXT: s_or_b32 s0, s2, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v2, s0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_endpgm
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bb:
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%i = zext i32 %arg to i64
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%i1 = getelementptr i32, ptr addrspace(1) %ptr, i64 %i
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%i2 = load <3 x i32>, ptr addrspace(1) %i1, align 4
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%i3 = extractelement <3 x i32> %i2, i32 0
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%i4 = extractelement <3 x i32> %i2, i32 1
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%i5 = extractelement <3 x i32> %i2, i32 2
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%i6 = or i32 %i3, %i4
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%i7 = or i32 %i5, %i6
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store i32 %i7, ptr addrspace(1) %ptr, align 4
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ret void
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}
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