e377dc4d38
The default maximum waves/EU returned by the family of `AMDGPUSubtarget::getWavesPerEU` is currently the maximum number of waves/EU supported by the subtarget (only a valid occupancy range in "amdgpu-waves-per-eu" may lower that maximum). This ignores maximum achievable occupancy imposed by flat workgroup size and LDS usage, resulting in situations where `AMDGPUSubtarget::getWavesPerEU` produces a maximum higher than the one from `AMDGPUSubtarget::getOccupancyWithWorkGroupSizes`. This limits the waves/EU range's maximum to the maximum achievable occupancy derived from flat workgroup sizes and LDS usage. This only has an impact on functions which restrict flat workgroup size with "amdgpu-flat-work-group-size", since the default range of flat workgroup sizes achieves the maximum number of waves/EU supported by the subtarget. Improvements to the handling of "amdgpu-waves-per-eu" are left for a follow up PR (e.g., I think the attribute should be able to lower the full range of waves/EU produced by these methods).
46 lines
1.7 KiB
LLVM
46 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Interleave loads and stores to fit into 9 VGPR limit.
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; This requires to avoid load/store clustering.
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; Reschedule the second scheduling region without clustering while
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; the first region is skipped.
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; GCN: global_load_dwordx4
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; GCN: global_store_dwordx4
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; GCN: global_load_dwordx4
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; GCN: global_store_dwordx4
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; GCN: global_load_dwordx4
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; GCN: global_store_dwordx4
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; GCN: NumVgprs: {{[0-9]$}}
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; GCN: ScratchSize: 0{{$}}
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define amdgpu_kernel void @load_store_max_9vgprs(ptr addrspace(1) nocapture noalias readonly %arg, ptr addrspace(1) nocapture noalias %arg1, i1 %cnd) #1 {
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%base = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i32 %id
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br i1 %cnd, label %bb1, label %bb2
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bb1:
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%tmp = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 1
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%tmp2 = load <4 x i32>, ptr addrspace(1) %tmp, align 4
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%tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 3
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%tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 4
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%tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %base, i32 5
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%tmp6 = load <4 x i32>, ptr addrspace(1) %tmp5, align 4
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store <4 x i32> %tmp2, ptr addrspace(1) %arg1, align 4
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%tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 3
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store <4 x i32> %tmp4, ptr addrspace(1) %tmp7, align 4
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%tmp8 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 5
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store <4 x i32> %tmp6, ptr addrspace(1) %tmp8, align 4
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br label %bb2
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bb2:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { "amdgpu-num-vgpr"="9" }
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