256343a0e9
Reverts llvm/llvm-project#81394 This reverts commit 3ac243bc0d7922d083af2cf025247b5698556062. It is not handling RSrc registers s0-s3 correctly. This leads to a broken test, where it expects s0-s3 as function argument and uses it as RSrc register as well. We need to re-visit the patch, but apparently we only want to have s0-s3 as argument registers if we don't need them as RSrc registers.
47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GISEL
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define amdgpu_gfx i32 @sink_scratch_pointer(ptr addrspace(5) %stack, i32 inreg %flag) {
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; GCN-LABEL: sink_scratch_pointer:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u32 s4, 0
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; GCN-NEXT: s_cbranch_scc0 .LBB0_2
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; GCN-NEXT: ; %bb.1: ; %bb2
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; GCN-NEXT: scratch_load_b32 v0, v0, off offset:-4
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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; GCN-NEXT: .LBB0_2: ; %bb1
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; GCN-NEXT: v_mov_b32_e32 v1, 1
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; GCN-NEXT: scratch_store_b32 v0, v1, off offset:-4
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: sink_scratch_pointer:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_cmp_lg_u32 s4, 0
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; GISEL-NEXT: s_cbranch_scc0 .LBB0_2
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; GISEL-NEXT: ; %bb.1: ; %bb2
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; GISEL-NEXT: scratch_load_b32 v0, v0, off offset:-4
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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; GISEL-NEXT: .LBB0_2: ; %bb1
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; GISEL-NEXT: v_mov_b32_e32 v1, 1
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; GISEL-NEXT: scratch_store_b32 v0, v1, off offset:-4
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; GISEL-NEXT: v_mov_b32_e32 v0, 0
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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%ptr = getelementptr inbounds i32, ptr addrspace(5) %stack, i32 -1
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%cond = icmp eq i32 %flag, 0
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br i1 %cond, label %bb1, label %bb2
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bb1:
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store i32 1, ptr addrspace(5) %ptr, align 4
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ret i32 0
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bb2:
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%value = load i32, ptr addrspace(5) %ptr, align 4
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ret i32 %value
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}
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