9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
65 lines
2.3 KiB
LLVM
65 lines
2.3 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}select0:
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; i64 select should be split into two i32 selects, and we shouldn't need
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; to use a shfit to extract the hi dword of the input.
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; GCN-NOT: s_lshr_b64
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; GCN: s_cselect_b32
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; GCN: s_cselect_b32
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define amdgpu_kernel void @select0(ptr addrspace(1) %out, i32 %cond, i64 %in) {
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entry:
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%0 = icmp ugt i32 %cond, 5
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%1 = select i1 %0, i64 0, i64 %in
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store i64 %1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}select_trunc_i64:
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; GCN: s_cselect_b32
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; GCN-NOT: s_cselect_b32
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define amdgpu_kernel void @select_trunc_i64(ptr addrspace(1) %out, i32 %cond, i64 %in) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%sel = select i1 %cmp, i64 0, i64 %in
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%trunc = trunc i64 %sel to i32
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store i32 %trunc, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}select_trunc_i64_2:
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; GCN: s_cselect_b32
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; GCN-NOT: s_cselect_b32
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define amdgpu_kernel void @select_trunc_i64_2(ptr addrspace(1) %out, i32 %cond, i64 %a, i64 %b) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%sel = select i1 %cmp, i64 %a, i64 %b
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%trunc = trunc i64 %sel to i32
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store i32 %trunc, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_select_trunc_i64_2:
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; GCN: s_cselect_b32
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; GCN-NOT: s_cselect_b32
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define amdgpu_kernel void @v_select_trunc_i64_2(ptr addrspace(1) %out, i32 %cond, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%a = load i64, ptr addrspace(1) %aptr, align 8
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%b = load i64, ptr addrspace(1) %bptr, align 8
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%sel = select i1 %cmp, i64 %a, i64 %b
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%trunc = trunc i64 %sel to i32
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store i32 %trunc, ptr addrspace(1) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_select_i64_split_imm:
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; GCN-DAG: s_cselect_b32
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; GCN-DAG: s_cselect_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @v_select_i64_split_imm(ptr addrspace(1) %out, i32 %cond, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%a = load i64, ptr addrspace(1) %aptr, align 8
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%b = load i64, ptr addrspace(1) %bptr, align 8
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%sel = select i1 %cmp, i64 %a, i64 270582939648 ; 63 << 32
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store i64 %sel, ptr addrspace(1) %out, align 8
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ret void
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}
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