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llvm-project/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
Brox Chen 6dbc01e801
[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#135078) 
This is a NFC patch.

This patch run a bulk update on CodeGen tests that are impacted by the
true16 features. This patch applies:
1. duplicate GFX11plus runlines and apply them with
"+mattr=+real-true16" and "+mattr=-real-true16"
2. update the test with the update script

For some GISEL runlines, the current CodeGen do not fully support the
true16 version. Still update the runlines, but comment out the failing
one, and added a "FIXME-TRUE16" comment to that test for easier
tracking. These test will be fixed in the following patches.

This is in a transition state that we support both
"+real-true16/-real-true16" in our code base. We plan to move to
"+real-true16" as default, and finally remove "-real-true16" mode and
test lines.
2025-04-23 13:06:52 -04:00

399 lines
15 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,HAWAII %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,FIJI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GFX11,GFX11-FAKE16 %s
define void @local_store_i56(ptr addrspace(3) %ptr, i56 %arg) #0 {
; CIVI-LABEL: local_store_i56:
; CIVI: ; %bb.0:
; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CIVI-NEXT: s_mov_b32 m0, -1
; CIVI-NEXT: ds_write_b16 v0, v2 offset:4
; CIVI-NEXT: ds_write_b32 v0, v1
; CIVI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; CIVI-NEXT: ds_write_b8 v0, v1 offset:6
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: local_store_i56:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:6
; GFX9-NEXT: ds_write_b16 v0, v2 offset:4
; GFX9-NEXT: ds_write_b32 v0, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: local_store_i56:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:6
; GFX10-NEXT: ds_write_b16 v0, v2 offset:4
; GFX10-NEXT: ds_write_b32 v0, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: local_store_i56:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: ds_store_b8_d16_hi v0, v2 offset:6
; GFX11-NEXT: ds_store_b16 v0, v2 offset:4
; GFX11-NEXT: ds_store_b32 v0, v1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
store i56 %arg, ptr addrspace(3) %ptr, align 8
ret void
}
define amdgpu_kernel void @local_store_i55(ptr addrspace(3) %ptr, i55 %arg) #0 {
; HAWAII-LABEL: local_store_i55:
; HAWAII: ; %bb.0:
; HAWAII-NEXT: s_add_i32 s12, s12, s17
; HAWAII-NEXT: s_or_b32 s0, s8, 14
; HAWAII-NEXT: s_mov_b32 flat_scratch_lo, s13
; HAWAII-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; HAWAII-NEXT: v_mov_b32_e32 v0, s0
; HAWAII-NEXT: v_mov_b32_e32 v1, s9
; HAWAII-NEXT: flat_load_ubyte v0, v[0:1]
; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x0
; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2
; HAWAII-NEXT: s_mov_b32 m0, -1
; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
; HAWAII-NEXT: v_mov_b32_e32 v1, s2
; HAWAII-NEXT: v_mov_b32_e32 v2, s1
; HAWAII-NEXT: v_mov_b32_e32 v3, s0
; HAWAII-NEXT: ds_write_b16 v1, v2 offset:4
; HAWAII-NEXT: s_waitcnt vmcnt(0)
; HAWAII-NEXT: v_and_b32_e32 v0, 0x7f, v0
; HAWAII-NEXT: ds_write_b8 v1, v0 offset:6
; HAWAII-NEXT: ds_write_b32 v1, v3
; HAWAII-NEXT: s_endpgm
;
; FIJI-LABEL: local_store_i55:
; FIJI: ; %bb.0:
; FIJI-NEXT: s_add_i32 s12, s12, s17
; FIJI-NEXT: s_or_b32 s0, s8, 14
; FIJI-NEXT: s_mov_b32 flat_scratch_lo, s13
; FIJI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; FIJI-NEXT: v_mov_b32_e32 v0, s0
; FIJI-NEXT: v_mov_b32_e32 v1, s9
; FIJI-NEXT: flat_load_ubyte v0, v[0:1]
; FIJI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; FIJI-NEXT: s_load_dword s2, s[8:9], 0x0
; FIJI-NEXT: s_mov_b32 m0, -1
; FIJI-NEXT: s_waitcnt lgkmcnt(0)
; FIJI-NEXT: s_and_b32 s3, s1, 0xffff
; FIJI-NEXT: v_mov_b32_e32 v1, s2
; FIJI-NEXT: v_mov_b32_e32 v2, s1
; FIJI-NEXT: v_mov_b32_e32 v3, s0
; FIJI-NEXT: ds_write_b16 v1, v2 offset:4
; FIJI-NEXT: s_waitcnt vmcnt(0)
; FIJI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; FIJI-NEXT: v_or_b32_e32 v0, s3, v0
; FIJI-NEXT: v_bfe_u32 v0, v0, 16, 7
; FIJI-NEXT: ds_write_b8 v1, v0 offset:6
; FIJI-NEXT: ds_write_b32 v1, v3
; FIJI-NEXT: s_endpgm
;
; GFX9-LABEL: local_store_i55:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_load_ubyte_d16_hi v0, v0, s[8:9] offset:14
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s3, s1, 0xffff
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v3, s0
; GFX9-NEXT: ds_write_b16 v1, v2 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
; GFX9-NEXT: ds_write_b8_d16_hi v1, v0 offset:6
; GFX9-NEXT: ds_write_b32 v1, v3
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: local_store_i55:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; GFX10-NEXT: s_load_dword s2, s[8:9], 0x0
; GFX10-NEXT: global_load_ubyte_d16_hi v0, v0, s[8:9] offset:14
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s3, s1, 0xffff
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_or_b32_e32 v0, s3, v0
; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
; GFX10-NEXT: ds_write_b16 v1, v2 offset:4
; GFX10-NEXT: ds_write_b8_d16_hi v1, v0 offset:6
; GFX10-NEXT: ds_write_b32 v1, v3
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: local_store_i55:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s3, s1, 0xffff
; GFX11-NEXT: v_mov_b32_e32 v1, s2
; GFX11-NEXT: global_load_d16_hi_u8 v0, v0, s[4:5] offset:14
; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_or_b32_e32 v0, s3, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
; GFX11-NEXT: ds_store_b8_d16_hi v1, v0 offset:6
; GFX11-NEXT: ds_store_b16 v1, v2 offset:4
; GFX11-NEXT: ds_store_b32 v1, v3
; GFX11-NEXT: s_endpgm
store i55 %arg, ptr addrspace(3) %ptr, align 8
ret void
}
define amdgpu_kernel void @local_store_i48(ptr addrspace(3) %ptr, i48 %arg) #0 {
; HAWAII-LABEL: local_store_i48:
; HAWAII: ; %bb.0:
; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x0
; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2
; HAWAII-NEXT: s_mov_b32 m0, -1
; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
; HAWAII-NEXT: v_mov_b32_e32 v0, s2
; HAWAII-NEXT: v_mov_b32_e32 v1, s1
; HAWAII-NEXT: v_mov_b32_e32 v2, s0
; HAWAII-NEXT: ds_write_b16 v0, v1 offset:4
; HAWAII-NEXT: ds_write_b32 v0, v2
; HAWAII-NEXT: s_endpgm
;
; FIJI-LABEL: local_store_i48:
; FIJI: ; %bb.0:
; FIJI-NEXT: s_load_dword s2, s[8:9], 0x0
; FIJI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; FIJI-NEXT: s_mov_b32 m0, -1
; FIJI-NEXT: s_waitcnt lgkmcnt(0)
; FIJI-NEXT: v_mov_b32_e32 v0, s2
; FIJI-NEXT: v_mov_b32_e32 v1, s1
; FIJI-NEXT: v_mov_b32_e32 v2, s0
; FIJI-NEXT: ds_write_b16 v0, v1 offset:4
; FIJI-NEXT: ds_write_b32 v0, v2
; FIJI-NEXT: s_endpgm
;
; GFX9-LABEL: local_store_i48:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: ds_write_b16 v0, v1 offset:4
; GFX9-NEXT: ds_write_b32 v0, v2
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: local_store_i48:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dword s2, s[8:9], 0x0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: ds_write_b16 v0, v1 offset:4
; GFX10-NEXT: ds_write_b32 v0, v2
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: local_store_i48:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: ds_store_b16 v0, v1 offset:4
; GFX11-NEXT: ds_store_b32 v0, v2
; GFX11-NEXT: s_endpgm
store i48 %arg, ptr addrspace(3) %ptr, align 8
ret void
}
define amdgpu_kernel void @local_store_i65(ptr addrspace(3) %ptr, i65 %arg) #0 {
; HAWAII-LABEL: local_store_i65:
; HAWAII: ; %bb.0:
; HAWAII-NEXT: s_load_dword s2, s[8:9], 0x4
; HAWAII-NEXT: s_load_dword s3, s[8:9], 0x0
; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2
; HAWAII-NEXT: s_mov_b32 m0, -1
; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
; HAWAII-NEXT: s_and_b32 s2, s2, 1
; HAWAII-NEXT: v_mov_b32_e32 v2, s3
; HAWAII-NEXT: v_mov_b32_e32 v0, s2
; HAWAII-NEXT: ds_write_b8 v2, v0 offset:8
; HAWAII-NEXT: v_mov_b32_e32 v0, s0
; HAWAII-NEXT: v_mov_b32_e32 v1, s1
; HAWAII-NEXT: ds_write_b64 v2, v[0:1]
; HAWAII-NEXT: s_endpgm
;
; FIJI-LABEL: local_store_i65:
; FIJI: ; %bb.0:
; FIJI-NEXT: s_load_dword s2, s[8:9], 0x10
; FIJI-NEXT: s_load_dword s3, s[8:9], 0x0
; FIJI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; FIJI-NEXT: s_mov_b32 m0, -1
; FIJI-NEXT: s_waitcnt lgkmcnt(0)
; FIJI-NEXT: s_and_b32 s2, s2, 1
; FIJI-NEXT: v_mov_b32_e32 v2, s3
; FIJI-NEXT: v_mov_b32_e32 v0, s2
; FIJI-NEXT: ds_write_b8 v2, v0 offset:8
; FIJI-NEXT: v_mov_b32_e32 v0, s0
; FIJI-NEXT: v_mov_b32_e32 v1, s1
; FIJI-NEXT: ds_write_b64 v2, v[0:1]
; FIJI-NEXT: s_endpgm
;
; GFX9-LABEL: local_store_i65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x10
; GFX9-NEXT: s_load_dword s3, s[8:9], 0x0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s3
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: ds_write_b8 v2, v3 offset:8
; GFX9-NEXT: ds_write_b64 v2, v[0:1]
; GFX9-NEXT: s_endpgm
;
; GFX10-LABEL: local_store_i65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dword s2, s[8:9], 0x10
; GFX10-NEXT: s_load_dword s3, s[8:9], 0x0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s2, s2, 1
; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: ds_write_b8 v2, v3 offset:8
; GFX10-NEXT: ds_write_b64 v2, v[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: local_store_i65:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x10
; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x0
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s2, s2, 1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v3, s2
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: ds_store_b8 v2, v3 offset:8
; GFX11-NEXT: ds_store_b64 v2, v[0:1]
; GFX11-NEXT: s_endpgm
store i65 %arg, ptr addrspace(3) %ptr, align 8
ret void
}
define void @local_store_i13(ptr addrspace(3) %ptr, i13 %arg) #0 {
; CIVI-LABEL: local_store_i13:
; CIVI: ; %bb.0:
; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CIVI-NEXT: v_and_b32_e32 v1, 0x1fff, v1
; CIVI-NEXT: s_mov_b32 m0, -1
; CIVI-NEXT: ds_write_b16 v0, v1
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: local_store_i13:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x1fff, v1
; GFX9-NEXT: ds_write_b16 v0, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: local_store_i13:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v1, 0x1fff, v1
; GFX10-NEXT: ds_write_b16 v0, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: local_store_i13:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x1fff, v1.l
; GFX11-TRUE16-NEXT: ds_store_b16 v0, v1
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: local_store_i13:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0x1fff, v1
; GFX11-FAKE16-NEXT: ds_store_b16 v0, v1
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
store i13 %arg, ptr addrspace(3) %ptr, align 8
ret void
}
define void @local_store_i17(ptr addrspace(3) %ptr, i17 %arg) #0 {
; CIVI-LABEL: local_store_i17:
; CIVI: ; %bb.0:
; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CIVI-NEXT: s_mov_b32 m0, -1
; CIVI-NEXT: ds_write_b16 v0, v1
; CIVI-NEXT: v_bfe_u32 v1, v1, 16, 1
; CIVI-NEXT: ds_write_b8 v0, v1 offset:2
; CIVI-NEXT: s_waitcnt lgkmcnt(0)
; CIVI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: local_store_i17:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ds_write_b16 v0, v1
; GFX9-NEXT: v_and_b32_e32 v1, 0x1ffff, v1
; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:2
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: local_store_i17:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v2, 0x1ffff, v1
; GFX10-NEXT: ds_write_b16 v0, v1
; GFX10-NEXT: ds_write_b8_d16_hi v0, v2 offset:2
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: local_store_i17:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v2, 0x1ffff, v1
; GFX11-NEXT: ds_store_b16 v0, v1
; GFX11-NEXT: ds_store_b8_d16_hi v0, v2 offset:2
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
store i17 %arg, ptr addrspace(3) %ptr, align 8
ret void
}
attributes #0 = { nounwind }
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