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llvm-project/llvm/test/CodeGen
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Roman Lebedev 358df06f4e
[X86] Improve matchBinaryShuffle()'s BLEND lowering with per-element all-zero/all-ones knowledge 
We can use `OR` instead of `BLEND` if either the element we are not picking is zero (or masked away);
or the element we are picking overwhelms (e.g. it's all-ones) whatever the element we are not picking:
https://alive2.llvm.org/ce/z/RKejao

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D109726
2021-09-17 19:13:33 +03:00
..
AArch64
Add a command-line flag to control the Swift extended async frame info.
2021-09-16 06:57:45 -07:00
AMDGPU
[AMDGPU] Inline non-kernel functions using extern lds
2021-09-16 10:58:51 -07:00
ARC
[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
2021-09-10 13:04:08 -07:00
ARM
[ARM] Mitigate the cve-2021-35465 security vulnurability.
2021-09-16 12:56:43 +01:00
AVR
[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'
2021-08-05 10:37:36 +08:00
BPF
[OpaquePtr] Forbid mixing typed and opaque pointers
2021-09-10 15:18:23 +02:00
Generic
Moved the test to X86 as it's x86 specific.
2021-08-31 14:48:29 -04:00
Hexagon
DAG: Fix incorrect folding of fmul -1 to fneg
2021-09-14 21:25:02 -04:00
Inputs
…
Lanai
[Lanai] implement wide immediate support
2021-09-10 10:54:43 +00:00
M68k
[M68k][test] Migrate the remaining fixup and relaxation tests
2021-09-04 16:27:13 -07:00
Mips
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
MIR
AMDGPU: Invert ABI attribute handling
2021-09-09 18:24:28 -04:00
MSP430
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NVPTX
[NVPTX] Simplify and generalize constant printer.
2021-09-09 11:30:19 -07:00
PowerPC
Revert "[PowerPC][ELF] make sure local variable space does not overlap with parameter save area"
2021-09-17 08:07:18 +00:00
RISCV
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
SPARC
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SystemZ
SystemZ: Tidy up a mir test
2021-08-10 13:56:54 -04:00
Thumb
[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)
2021-09-07 15:42:43 +08:00
Thumb2
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
VE
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WebAssembly
Revert "[WebAssembly] Rethrow longjmp in EH handling if EmSjLj is enabled"
2021-09-14 12:59:42 -07:00
WinCFGuard
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WinEH
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
X86
[X86] Improve matchBinaryShuffle()'s BLEND lowering with per-element all-zero/all-ones knowledge
2021-09-17 19:13:33 +03:00
XCore
…