d57bba7cf8
To accommodate frame layouts that have both fixed and scalable objects on the stack, describing a stack location or offset using a pointer + uint64_t is not sufficient. For this reason, we've introduced the StackOffset class, which models both the fixed- and scalable sized offsets. The TargetFrameLowering::getFrameIndexReference is made to return a StackOffset, so that this can be used in other interfaces, such as to eliminate frame indices in PEI or to emit Debug locations for variables on the stack. This patch is purely mechanical and doesn't change the behaviour of how the result of this function is used for fixed-sized offsets. The patch adds various checks to assert that the offset has no scalable component, as frame offsets with a scalable component are not yet supported in various places. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D90018
378 lines
14 KiB
C++
378 lines
14 KiB
C++
//===-- VEFrameLowering.cpp - VE Frame Information ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the VE implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "VEFrameLowering.h"
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#include "VEInstrInfo.h"
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#include "VEMachineFunctionInfo.h"
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#include "VESubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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VEFrameLowering::VEFrameLowering(const VESubtarget &ST)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(16), 0,
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Align(16)),
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STI(ST) {}
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void VEFrameLowering::emitPrologueInsns(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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uint64_t NumBytes,
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bool RequireFPUpdate) const {
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DebugLoc dl;
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const VEInstrInfo &TII =
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*static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
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// Insert following codes here as prologue
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//
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// st %fp, 0(,%sp)
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// st %lr, 8(,%sp)
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// st %got, 24(,%sp)
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// st %plt, 32(,%sp)
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// st %s17, 40(,%sp) iff this function is using s17 as BP
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// or %fp, 0, %sp
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BuildMI(MBB, MBBI, dl, TII.get(VE::STrii))
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(0)
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.addReg(VE::SX9);
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BuildMI(MBB, MBBI, dl, TII.get(VE::STrii))
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(8)
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.addReg(VE::SX10);
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BuildMI(MBB, MBBI, dl, TII.get(VE::STrii))
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(24)
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.addReg(VE::SX15);
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BuildMI(MBB, MBBI, dl, TII.get(VE::STrii))
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(32)
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.addReg(VE::SX16);
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if (hasBP(MF))
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BuildMI(MBB, MBBI, dl, TII.get(VE::STrii))
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(40)
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.addReg(VE::SX17);
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BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX9)
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.addReg(VE::SX11)
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.addImm(0);
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}
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void VEFrameLowering::emitEpilogueInsns(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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uint64_t NumBytes,
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bool RequireFPUpdate) const {
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DebugLoc dl;
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const VEInstrInfo &TII =
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*static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
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// Insert following codes here as epilogue
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//
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// or %sp, 0, %fp
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// ld %s17, 40(,%sp) iff this function is using s17 as BP
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// ld %got, 32(,%sp)
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// ld %plt, 24(,%sp)
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// ld %lr, 8(,%sp)
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// ld %fp, 0(,%sp)
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BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX11)
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.addReg(VE::SX9)
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.addImm(0);
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if (hasBP(MF))
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BuildMI(MBB, MBBI, dl, TII.get(VE::LDrii), VE::SX17)
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(40);
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BuildMI(MBB, MBBI, dl, TII.get(VE::LDrii), VE::SX16)
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(32);
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BuildMI(MBB, MBBI, dl, TII.get(VE::LDrii), VE::SX15)
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(24);
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BuildMI(MBB, MBBI, dl, TII.get(VE::LDrii), VE::SX10)
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(8);
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BuildMI(MBB, MBBI, dl, TII.get(VE::LDrii), VE::SX9)
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.addReg(VE::SX11)
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.addImm(0)
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.addImm(0);
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}
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void VEFrameLowering::emitSPAdjustment(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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int64_t NumBytes,
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MaybeAlign MaybeAlign) const {
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DebugLoc dl;
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const VEInstrInfo &TII =
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*static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
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if (NumBytes >= -64 && NumBytes < 63) {
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BuildMI(MBB, MBBI, dl, TII.get(VE::ADDSLri), VE::SX11)
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.addReg(VE::SX11)
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.addImm(NumBytes);
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return;
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}
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// Emit following codes. This clobbers SX13 which we always know is
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// available here.
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// lea %s13,%lo(NumBytes)
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// and %s13,%s13,(32)0
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// lea.sl %sp,%hi(NumBytes)(%sp, %s13)
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BuildMI(MBB, MBBI, dl, TII.get(VE::LEAzii), VE::SX13)
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.addImm(0)
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.addImm(0)
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.addImm(Lo_32(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(VE::ANDrm), VE::SX13)
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.addReg(VE::SX13)
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.addImm(M0(32));
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BuildMI(MBB, MBBI, dl, TII.get(VE::LEASLrri), VE::SX11)
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.addReg(VE::SX11)
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.addReg(VE::SX13)
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.addImm(Hi_32(NumBytes));
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if (MaybeAlign) {
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// and %sp, %sp, Align-1
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BuildMI(MBB, MBBI, dl, TII.get(VE::ANDrm), VE::SX11)
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.addReg(VE::SX11)
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.addImm(M1(64 - Log2_64(MaybeAlign.valueOrOne().value())));
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}
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}
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void VEFrameLowering::emitSPExtend(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const {
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DebugLoc dl;
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const VEInstrInfo &TII =
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*static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
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// Emit following codes. It is not possible to insert multiple
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// BasicBlocks in PEI pass, so we emit two pseudo instructions here.
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//
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// EXTEND_STACK // pseudo instrcution
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// EXTEND_STACK_GUARD // pseudo instrcution
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//
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// EXTEND_STACK pseudo will be converted by ExpandPostRA pass into
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// following instructions with multiple basic blocks later.
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//
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// thisBB:
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// brge.l.t %sp, %sl, sinkBB
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// syscallBB:
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// ld %s61, 0x18(, %tp) // load param area
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// or %s62, 0, %s0 // spill the value of %s0
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// lea %s63, 0x13b // syscall # of grow
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// shm.l %s63, 0x0(%s61) // store syscall # at addr:0
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// shm.l %sl, 0x8(%s61) // store old limit at addr:8
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// shm.l %sp, 0x10(%s61) // store new limit at addr:16
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// monc // call monitor
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// or %s0, 0, %s62 // restore the value of %s0
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// sinkBB:
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//
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// EXTEND_STACK_GUARD pseudo will be simply eliminated by ExpandPostRA
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// pass. This pseudo is required to be at the next of EXTEND_STACK
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// pseudo in order to protect iteration loop in ExpandPostRA.
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BuildMI(MBB, MBBI, dl, TII.get(VE::EXTEND_STACK));
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BuildMI(MBB, MBBI, dl, TII.get(VE::EXTEND_STACK_GUARD));
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}
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void VEFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineFrameInfo &MFI = MF.getFrameInfo();
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const VEInstrInfo &TII = *STI.getInstrInfo();
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const VERegisterInfo &RegInfo = *STI.getRegisterInfo();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc dl;
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bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
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// FIXME: unfortunately, returning false from canRealignStack
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// actually just causes needsStackRealignment to return false,
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// rather than reporting an error, as would be sensible. This is
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// poor, but fixing that bogosity is going to be a large project.
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// For now, just see if it's lied, and report an error here.
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if (!NeedsStackRealignment && MFI.getMaxAlign() > getStackAlign())
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report_fatal_error("Function \"" + Twine(MF.getName()) +
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"\" required "
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"stack re-alignment, but LLVM couldn't handle it "
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"(probably because it has a dynamic alloca).");
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// Get the number of bytes to allocate from the FrameInfo
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uint64_t NumBytes = MFI.getStackSize();
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// The VE ABI requires a reserved 176 bytes area at the top
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// of stack as described in VESubtarget.cpp. So, we adjust it here.
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NumBytes = STI.getAdjustedFrameSize(NumBytes);
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// Finally, ensure that the size is sufficiently aligned for the
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// data on the stack.
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NumBytes = alignTo(NumBytes, MFI.getMaxAlign());
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// Update stack size with corrected value.
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MFI.setStackSize(NumBytes);
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// Emit Prologue instructions to save %lr
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emitPrologueInsns(MF, MBB, MBBI, NumBytes, true);
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// Emit stack adjust instructions
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MaybeAlign RuntimeAlign =
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NeedsStackRealignment ? MaybeAlign(MFI.getMaxAlign()) : None;
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emitSPAdjustment(MF, MBB, MBBI, -(int64_t)NumBytes, RuntimeAlign);
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if (hasBP(MF)) {
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// Copy SP to BP.
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BuildMI(MBB, MBBI, dl, TII.get(VE::ORri), VE::SX17)
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.addReg(VE::SX11)
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.addImm(0);
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}
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// Emit stack extend instructions
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emitSPExtend(MF, MBB, MBBI);
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Register RegFP = RegInfo.getDwarfRegNum(VE::SX9, true);
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// Emit ".cfi_def_cfa_register 30".
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unsigned CFIIndex =
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MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, RegFP));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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// Emit ".cfi_window_save".
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CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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MachineBasicBlock::iterator VEFrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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MachineInstr &MI = *I;
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int64_t Size = MI.getOperand(0).getImm();
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if (MI.getOpcode() == VE::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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emitSPAdjustment(MF, MBB, I, Size);
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}
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return MBB.erase(I);
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}
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void VEFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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DebugLoc dl = MBBI->getDebugLoc();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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uint64_t NumBytes = MFI.getStackSize();
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// Emit Epilogue instructions to restore %lr
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emitEpilogueInsns(MF, MBB, MBBI, NumBytes, true);
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas
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// or if frame pointer elimination is disabled. For the case of VE, we don't
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// implement FP eliminator yet, but we returns false from this function to
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// not refer fp from generated code.
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bool VEFrameLowering::hasFP(const MachineFunction &MF) const {
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const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
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MFI.isFrameAddressTaken();
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}
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bool VEFrameLowering::hasBP(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetRegisterInfo *TRI = STI.getRegisterInfo();
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return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
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}
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StackOffset VEFrameLowering::getFrameIndexReference(const MachineFunction &MF,
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int FI,
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Register &FrameReg) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const VERegisterInfo *RegInfo = STI.getRegisterInfo();
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const VEMachineFunctionInfo *FuncInfo = MF.getInfo<VEMachineFunctionInfo>();
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bool isFixed = MFI.isFixedObjectIndex(FI);
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int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI);
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if (FuncInfo->isLeafProc()) {
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// If there's a leaf proc, all offsets need to be %sp-based,
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// because we haven't caused %fp to actually point to our frame.
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FrameReg = VE::SX11; // %sp
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return StackOffset::getFixed(FrameOffset +
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MF.getFrameInfo().getStackSize());
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}
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if (RegInfo->needsStackRealignment(MF) && !isFixed) {
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// If there is dynamic stack realignment, all local object
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// references need to be via %sp or %s17 (bp), to take account
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// of the re-alignment.
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if (hasBP(MF))
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FrameReg = VE::SX17; // %bp
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else
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FrameReg = VE::SX11; // %sp
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return StackOffset::getFixed(FrameOffset +
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MF.getFrameInfo().getStackSize());
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}
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// Finally, default to using %fp.
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FrameReg = RegInfo->getFrameRegister(MF);
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return StackOffset::getFixed(FrameOffset);
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}
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bool VEFrameLowering::isLeafProc(MachineFunction &MF) const {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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return !MFI.hasCalls() // No calls
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&& !MRI.isPhysRegUsed(VE::SX18) // Registers within limits
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// (s18 is first CSR)
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&& !MRI.isPhysRegUsed(VE::SX11) // %sp un-used
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&& !hasFP(MF); // Don't need %fp
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}
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void VEFrameLowering::determineCalleeSaves(MachineFunction &MF,
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BitVector &SavedRegs,
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RegScavenger *RS) const {
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TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
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if (isLeafProc(MF)) {
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VEMachineFunctionInfo *MFI = MF.getInfo<VEMachineFunctionInfo>();
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MFI->setLeafProc(true);
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}
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}
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