1d0005a69a
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than just `KnownBits` in the future
58 lines
1.8 KiB
C++
58 lines
1.8 KiB
C++
//===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/CodeGen/Register.h"
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#include <utility>
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namespace llvm {
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class MachineRegisterInfo;
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class GCNSubtarget;
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class GISelValueTracking;
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class LLT;
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class MachineFunction;
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class MachineIRBuilder;
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class RegisterBankInfo;
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namespace AMDGPU {
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/// Returns base register and constant offset.
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std::pair<Register, unsigned>
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getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
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GISelValueTracking *ValueTracking = nullptr,
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bool CheckNUW = false);
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// Currently finds S32/S64 lane masks that can be declared as divergent by
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// uniformity analysis (all are phis at the moment).
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// These are defined as i32/i64 in some IR intrinsics (not as i1).
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// Tablegen forces(via telling that lane mask IR intrinsics are uniform) most of
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// S32/S64 lane masks to be uniform, as this results in them ending up with sgpr
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// reg class after instruction-select, don't search for all of them.
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class IntrinsicLaneMaskAnalyzer {
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SmallDenseSet<Register, 8> S32S64LaneMask;
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MachineRegisterInfo &MRI;
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public:
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IntrinsicLaneMaskAnalyzer(MachineFunction &MF);
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bool isS32S64LaneMask(Register Reg) const;
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private:
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void initLaneMaskIntrinsics(MachineFunction &MF);
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};
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void buildReadAnyLane(MachineIRBuilder &B, Register SgprDst, Register VgprSrc,
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const RegisterBankInfo &RBI);
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}
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}
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#endif
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