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llvm-project/llvm/test/CodeGen
History
Craig Topper 391b0ba603 [RISCV] Override TargetLowering::hasAndNot for Zbb. 
Differential Revision: https://reviews.llvm.org/D113937
2021-11-15 18:44:07 -08:00
..
AArch64
[AArch64][SVE] Break false dependencies for inactive lanes of FP unary operations
2021-11-15 09:15:21 +00:00
AMDGPU
AMDGPU: Mark prolog/epilog SCC defs as dead
2021-11-15 21:35:06 -05:00
ARC
[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
2021-09-10 13:04:08 -07:00
ARM
[ARM] implement support for TLS register based stack protector
2021-11-09 18:19:47 +01:00
AVR
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
BPF
BPF: change btf_type_tag BTF output format
2021-11-09 11:34:25 -08:00
CSKY
[CSKY] First patch to construct codegen infra and generate first add instruction
2021-11-01 10:06:56 +08:00
Generic
[asm] Correctly handle special names in variants
2021-11-15 15:37:09 -05:00
Hexagon
[LiveIntervals] Update subranges in processTiedPairs
2021-11-11 12:24:59 +00:00
Inputs
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Lanai
[Lanai] implement wide immediate support
2021-09-10 10:54:43 +00:00
M68k
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Mips
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
MIR
[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
2021-11-07 15:06:54 +00:00
MSP430
[llvm-readobj] Support dumping of MSP430 ELF attributes
2021-09-28 00:56:11 +03:00
NVPTX
[NVPTX] Add imm variants for surface and texture instructions
2021-11-10 19:05:03 +03:00
PowerPC
[PowerPC] Fix 32bit vector insert instructions for ISA3.1
2021-11-15 14:36:39 -06:00
RISCV
[RISCV] Override TargetLowering::hasAndNot for Zbb.
2021-11-15 18:44:07 -08:00
SPARC
[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers
2021-11-14 19:59:52 +01:00
SystemZ
[SystemZ] Improvement of emitMemMemWrapper()
2021-10-26 17:03:01 +02:00
Thumb
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
Thumb2
[ARM] Fix GatherScatter AddLikeOr condition
2021-11-15 09:44:41 +00:00
VE
[VE][NFC] correct bitmasking in popcnt expansion test
2021-10-25 13:55:58 +02:00
WebAssembly
[WebAssembly] Add prototype relaxed float to int trunc instructions
2021-10-28 14:01:53 -07:00
WinCFGuard
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WinEH
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X86
[X86] Fix crash with inline asm using wrong register name
2021-11-16 10:38:12 +08:00
XCore
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