3a4b351ba1
This introduces a new `ptrtoaddr` instruction which is similar to `ptrtoint` but has two differences: 1) Unlike `ptrtoint`, `ptrtoaddr` does not capture provenance 2) `ptrtoaddr` only extracts (and then extends/truncates) the low index-width bits of the pointer For most architectures, difference 2) does not matter since index (address) width and pointer representation width are the same, but this does make a difference for architectures that have pointers that aren't just plain integer addresses such as AMDGPU fat pointers or CHERI capabilities. This commit introduces textual and bitcode IR support as well as basic code generation, but optimization passes do not handle the new instruction yet so it may result in worse code than using ptrtoint. Follow-up changes will update capture tracking, etc. for the new instruction. RFC: https://discourse.llvm.org/t/clarifiying-the-semantics-of-ptrtoint/83987/54 Reviewed By: nikic Pull Request: https://github.com/llvm/llvm-project/pull/139357
260 lines
9.4 KiB
C++
260 lines
9.4 KiB
C++
//===- Legality.cpp -------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h"
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#include "llvm/SandboxIR/Instruction.h"
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#include "llvm/SandboxIR/Operator.h"
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#include "llvm/SandboxIR/Utils.h"
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#include "llvm/SandboxIR/Value.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h"
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#include "llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h"
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namespace llvm::sandboxir {
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#ifndef NDEBUG
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void ShuffleMask::dump() const {
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print(dbgs());
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dbgs() << "\n";
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}
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void LegalityResult::dump() const {
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print(dbgs());
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dbgs() << "\n";
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}
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#endif // NDEBUG
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std::optional<ResultReason>
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LegalityAnalysis::notVectorizableBasedOnOpcodesAndTypes(
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ArrayRef<Value *> Bndl) {
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auto *I0 = cast<Instruction>(Bndl[0]);
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auto Opcode = I0->getOpcode();
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// If they have different opcodes, then we cannot form a vector (for now).
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if (any_of(drop_begin(Bndl), [Opcode](Value *V) {
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return cast<Instruction>(V)->getOpcode() != Opcode;
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}))
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return ResultReason::DiffOpcodes;
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// If not the same scalar type, Pack. This will accept scalars and vectors as
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// long as the element type is the same.
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Type *ElmTy0 = VecUtils::getElementType(Utils::getExpectedType(I0));
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if (any_of(drop_begin(Bndl), [ElmTy0](Value *V) {
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return VecUtils::getElementType(Utils::getExpectedType(V)) != ElmTy0;
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}))
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return ResultReason::DiffTypes;
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// TODO: Allow vectorization of instrs with different flags as long as we
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// change them to the least common one.
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// For now pack if differnt FastMathFlags.
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if (isa<FPMathOperator>(I0)) {
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FastMathFlags FMF0 = cast<Instruction>(Bndl[0])->getFastMathFlags();
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if (any_of(drop_begin(Bndl), [FMF0](auto *V) {
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return cast<Instruction>(V)->getFastMathFlags() != FMF0;
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}))
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return ResultReason::DiffMathFlags;
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}
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// TODO: Allow vectorization by using common flags.
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// For now Pack if they don't have the same wrap flags.
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bool CanHaveWrapFlags =
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isa<OverflowingBinaryOperator>(I0) || isa<TruncInst>(I0);
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if (CanHaveWrapFlags) {
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bool NUW0 = I0->hasNoUnsignedWrap();
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bool NSW0 = I0->hasNoSignedWrap();
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if (any_of(drop_begin(Bndl), [NUW0, NSW0](auto *V) {
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return cast<Instruction>(V)->hasNoUnsignedWrap() != NUW0 ||
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cast<Instruction>(V)->hasNoSignedWrap() != NSW0;
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})) {
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return ResultReason::DiffWrapFlags;
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}
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}
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// Now we need to do further checks for specific opcodes.
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switch (Opcode) {
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case Instruction::Opcode::ZExt:
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case Instruction::Opcode::SExt:
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case Instruction::Opcode::FPToUI:
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case Instruction::Opcode::FPToSI:
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case Instruction::Opcode::FPExt:
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case Instruction::Opcode::PtrToAddr:
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case Instruction::Opcode::PtrToInt:
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case Instruction::Opcode::IntToPtr:
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case Instruction::Opcode::SIToFP:
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case Instruction::Opcode::UIToFP:
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case Instruction::Opcode::Trunc:
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case Instruction::Opcode::FPTrunc:
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case Instruction::Opcode::BitCast: {
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// We have already checked that they are of the same opcode.
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assert(all_of(Bndl,
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[Opcode](Value *V) {
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return cast<Instruction>(V)->getOpcode() == Opcode;
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}) &&
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"Different opcodes, should have early returned!");
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// But for these opcodes we should also check the operand type.
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Type *FromTy0 = Utils::getExpectedType(I0->getOperand(0));
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if (any_of(drop_begin(Bndl), [FromTy0](Value *V) {
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return Utils::getExpectedType(cast<User>(V)->getOperand(0)) !=
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FromTy0;
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}))
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return ResultReason::DiffTypes;
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return std::nullopt;
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}
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case Instruction::Opcode::FCmp:
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case Instruction::Opcode::ICmp: {
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// We need the same predicate..
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auto Pred0 = cast<CmpInst>(I0)->getPredicate();
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bool Same = all_of(Bndl, [Pred0](Value *V) {
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return cast<CmpInst>(V)->getPredicate() == Pred0;
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});
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if (Same)
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return std::nullopt;
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return ResultReason::DiffOpcodes;
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}
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case Instruction::Opcode::Select: {
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auto *Sel0 = cast<SelectInst>(Bndl[0]);
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auto *Cond0 = Sel0->getCondition();
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if (VecUtils::getNumLanes(Cond0) != VecUtils::getNumLanes(Sel0))
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// TODO: For now we don't vectorize if the lanes in the condition don't
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// match those of the select instruction.
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return ResultReason::Unimplemented;
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return std::nullopt;
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}
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case Instruction::Opcode::FNeg:
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case Instruction::Opcode::Add:
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case Instruction::Opcode::FAdd:
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case Instruction::Opcode::Sub:
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case Instruction::Opcode::FSub:
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case Instruction::Opcode::Mul:
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case Instruction::Opcode::FMul:
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case Instruction::Opcode::FRem:
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case Instruction::Opcode::UDiv:
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case Instruction::Opcode::SDiv:
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case Instruction::Opcode::FDiv:
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case Instruction::Opcode::URem:
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case Instruction::Opcode::SRem:
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case Instruction::Opcode::Shl:
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case Instruction::Opcode::LShr:
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case Instruction::Opcode::AShr:
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case Instruction::Opcode::And:
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case Instruction::Opcode::Or:
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case Instruction::Opcode::Xor:
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return std::nullopt;
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case Instruction::Opcode::Load:
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if (VecUtils::areConsecutive<LoadInst>(Bndl, SE, DL))
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return std::nullopt;
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return ResultReason::NotConsecutive;
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case Instruction::Opcode::Store:
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if (VecUtils::areConsecutive<StoreInst>(Bndl, SE, DL))
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return std::nullopt;
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return ResultReason::NotConsecutive;
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case Instruction::Opcode::PHI:
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return ResultReason::Unimplemented;
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case Instruction::Opcode::Opaque:
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return ResultReason::Unimplemented;
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case Instruction::Opcode::Br:
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case Instruction::Opcode::Ret:
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case Instruction::Opcode::AddrSpaceCast:
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case Instruction::Opcode::InsertElement:
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case Instruction::Opcode::InsertValue:
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case Instruction::Opcode::ExtractElement:
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case Instruction::Opcode::ExtractValue:
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case Instruction::Opcode::ShuffleVector:
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case Instruction::Opcode::Call:
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case Instruction::Opcode::GetElementPtr:
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case Instruction::Opcode::Switch:
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return ResultReason::Unimplemented;
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case Instruction::Opcode::VAArg:
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case Instruction::Opcode::Freeze:
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case Instruction::Opcode::Fence:
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case Instruction::Opcode::Invoke:
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case Instruction::Opcode::CallBr:
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case Instruction::Opcode::LandingPad:
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case Instruction::Opcode::CatchPad:
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case Instruction::Opcode::CleanupPad:
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case Instruction::Opcode::CatchRet:
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case Instruction::Opcode::CleanupRet:
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case Instruction::Opcode::Resume:
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case Instruction::Opcode::CatchSwitch:
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case Instruction::Opcode::AtomicRMW:
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case Instruction::Opcode::AtomicCmpXchg:
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case Instruction::Opcode::Alloca:
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case Instruction::Opcode::Unreachable:
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return ResultReason::Infeasible;
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}
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return std::nullopt;
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}
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CollectDescr
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LegalityAnalysis::getHowToCollectValues(ArrayRef<Value *> Bndl) const {
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SmallVector<CollectDescr::ExtractElementDescr, 4> Vec;
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Vec.reserve(Bndl.size());
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for (auto [Elm, V] : enumerate(Bndl)) {
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if (auto *VecOp = IMaps.getVectorForOrig(V)) {
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// If there is a vector containing `V`, then get the lane it came from.
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std::optional<int> ExtractIdxOpt = IMaps.getOrigLane(VecOp, V);
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// This could be a vector, like <2 x float> in which case the mask needs
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// to enumerate all lanes.
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for (unsigned Ln = 0, Lanes = VecUtils::getNumLanes(V); Ln != Lanes; ++Ln)
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Vec.emplace_back(VecOp, ExtractIdxOpt ? *ExtractIdxOpt + Ln : -1);
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} else {
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Vec.emplace_back(V);
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}
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}
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return CollectDescr(std::move(Vec));
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}
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const LegalityResult &LegalityAnalysis::canVectorize(ArrayRef<Value *> Bndl,
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bool SkipScheduling) {
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// If Bndl contains values other than instructions, we need to Pack.
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if (any_of(Bndl, [](auto *V) { return !isa<Instruction>(V); }))
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return createLegalityResult<Pack>(ResultReason::NotInstructions);
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// Pack if not in the same BB.
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auto *BB = cast<Instruction>(Bndl[0])->getParent();
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if (any_of(drop_begin(Bndl),
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[BB](auto *V) { return cast<Instruction>(V)->getParent() != BB; }))
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return createLegalityResult<Pack>(ResultReason::DiffBBs);
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// Pack if instructions repeat, i.e., require some sort of broadcast.
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SmallPtrSet<Value *, 8> Unique(llvm::from_range, Bndl);
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if (Unique.size() != Bndl.size())
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return createLegalityResult<Pack>(ResultReason::RepeatedInstrs);
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auto CollectDescrs = getHowToCollectValues(Bndl);
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if (CollectDescrs.hasVectorInputs()) {
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if (auto ValueShuffleOpt = CollectDescrs.getSingleInput()) {
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auto [Vec, Mask] = *ValueShuffleOpt;
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if (Mask.isIdentity())
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return createLegalityResult<DiamondReuse>(Vec);
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return createLegalityResult<DiamondReuseWithShuffle>(Vec, Mask);
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}
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return createLegalityResult<DiamondReuseMultiInput>(
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std::move(CollectDescrs));
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}
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if (auto ReasonOpt = notVectorizableBasedOnOpcodesAndTypes(Bndl))
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return createLegalityResult<Pack>(*ReasonOpt);
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if (!SkipScheduling) {
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// TODO: Try to remove the IBndl vector.
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SmallVector<Instruction *, 8> IBndl;
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IBndl.reserve(Bndl.size());
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for (auto *V : Bndl)
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IBndl.push_back(cast<Instruction>(V));
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if (!Sched.trySchedule(IBndl))
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return createLegalityResult<Pack>(ResultReason::CantSchedule);
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}
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return createLegalityResult<Widen>();
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}
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void LegalityAnalysis::clear() {
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Sched.clear();
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IMaps.clear();
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}
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} // namespace llvm::sandboxir
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