2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
352 lines
11 KiB
TableGen
352 lines
11 KiB
TableGen
//===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the symbolic operands permitted for various kinds of
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// RISC-V system instruction.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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//===----------------------------------------------------------------------===//
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// CSR (control and status register read/write) instruction options.
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//===----------------------------------------------------------------------===//
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class SysReg<string name, bits<12> op> {
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string Name = name;
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bits<12> Encoding = op;
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// FIXME: add these additional fields when needed.
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// Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
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// Privilege Mode: User = 0, System = 1 or Machine = 3.
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// bits<2> ReadWrite = op{11 - 10};
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// bits<2> XMode = op{9 - 8};
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// Check Extra field name and what bits 7-6 correspond to.
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// bits<2> Extra = op{7 - 6};
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// Register number without the privilege bits.
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// bits<6> Number = op{5 - 0};
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code FeaturesRequired = [{ {} }];
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bit isRV32Only = 0;
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}
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def SysRegsList : GenericTable {
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let FilterClass = "SysReg";
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// FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
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let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ];
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let PrimaryKey = [ "Encoding" ];
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let PrimaryKeyName = "lookupSysRegByEncoding";
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}
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def lookupSysRegByName : SearchIndex {
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let Table = SysRegsList;
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let Key = [ "Name" ];
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}
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// The following CSR encodings match those given in Tables 2.2,
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// 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual
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// Volume II: Privileged Architecture.
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//===--------------------------
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// User Trap Setup
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//===--------------------------
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def : SysReg<"ustatus", 0x000>;
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def : SysReg<"uie", 0x004>;
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def : SysReg<"utvec", 0x005>;
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//===--------------------------
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// User Trap Handling
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//===--------------------------
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def : SysReg<"uscratch", 0x040>;
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def : SysReg<"uepc", 0x041>;
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def : SysReg<"ucause", 0x042>;
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def : SysReg<"utval", 0x043>;
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def : SysReg<"uip", 0x044>;
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//===--------------------------
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// User Floating-Point CSRs
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//===--------------------------
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let FeaturesRequired = [{ {RISCV::FeatureStdExtF} }] in {
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def : SysReg<"fflags", 0x001>;
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def : SysReg<"frm", 0x002>;
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def : SysReg<"fcsr", 0x003>;
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}
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//===--------------------------
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// User Counter/Timers
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//===--------------------------
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def : SysReg<"cycle", 0xC00>;
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def : SysReg<"time", 0xC01>;
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def : SysReg<"instret", 0xC02>;
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def : SysReg<"hpmcounter3", 0xC03>;
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def : SysReg<"hpmcounter4", 0xC04>;
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def : SysReg<"hpmcounter5", 0xC05>;
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def : SysReg<"hpmcounter6", 0xC06>;
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def : SysReg<"hpmcounter7", 0xC07>;
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def : SysReg<"hpmcounter8", 0xC08>;
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def : SysReg<"hpmcounter9", 0xC09>;
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def : SysReg<"hpmcounter10", 0xC0A>;
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def : SysReg<"hpmcounter11", 0xC0B>;
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def : SysReg<"hpmcounter12", 0xC0C>;
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def : SysReg<"hpmcounter13", 0xC0D>;
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def : SysReg<"hpmcounter14", 0xC0E>;
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def : SysReg<"hpmcounter15", 0xC0F>;
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def : SysReg<"hpmcounter16", 0xC10>;
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def : SysReg<"hpmcounter17", 0xC11>;
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def : SysReg<"hpmcounter18", 0xC12>;
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def : SysReg<"hpmcounter19", 0xC13>;
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def : SysReg<"hpmcounter20", 0xC14>;
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def : SysReg<"hpmcounter21", 0xC15>;
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def : SysReg<"hpmcounter22", 0xC16>;
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def : SysReg<"hpmcounter23", 0xC17>;
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def : SysReg<"hpmcounter24", 0xC18>;
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def : SysReg<"hpmcounter25", 0xC19>;
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def : SysReg<"hpmcounter26", 0xC1A>;
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def : SysReg<"hpmcounter27", 0xC1B>;
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def : SysReg<"hpmcounter28", 0xC1C>;
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def : SysReg<"hpmcounter29", 0xC1D>;
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def : SysReg<"hpmcounter30", 0xC1E>;
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def : SysReg<"hpmcounter31", 0xC1F>;
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let isRV32Only = 1 in {
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def: SysReg<"cycleh", 0xC80>;
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def: SysReg<"timeh", 0xC81>;
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def: SysReg<"instreth", 0xC82>;
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def: SysReg<"hpmcounter3h", 0xC83>;
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def: SysReg<"hpmcounter4h", 0xC84>;
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def: SysReg<"hpmcounter5h", 0xC85>;
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def: SysReg<"hpmcounter6h", 0xC86>;
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def: SysReg<"hpmcounter7h", 0xC87>;
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def: SysReg<"hpmcounter8h", 0xC88>;
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def: SysReg<"hpmcounter9h", 0xC89>;
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def: SysReg<"hpmcounter10h", 0xC8A>;
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def: SysReg<"hpmcounter11h", 0xC8B>;
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def: SysReg<"hpmcounter12h", 0xC8C>;
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def: SysReg<"hpmcounter13h", 0xC8D>;
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def: SysReg<"hpmcounter14h", 0xC8E>;
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def: SysReg<"hpmcounter15h", 0xC8F>;
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def: SysReg<"hpmcounter16h", 0xC90>;
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def: SysReg<"hpmcounter17h", 0xC91>;
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def: SysReg<"hpmcounter18h", 0xC92>;
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def: SysReg<"hpmcounter19h", 0xC93>;
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def: SysReg<"hpmcounter20h", 0xC94>;
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def: SysReg<"hpmcounter21h", 0xC95>;
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def: SysReg<"hpmcounter22h", 0xC96>;
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def: SysReg<"hpmcounter23h", 0xC97>;
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def: SysReg<"hpmcounter24h", 0xC98>;
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def: SysReg<"hpmcounter25h", 0xC99>;
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def: SysReg<"hpmcounter26h", 0xC9A>;
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def: SysReg<"hpmcounter27h", 0xC9B>;
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def: SysReg<"hpmcounter28h", 0xC9C>;
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def: SysReg<"hpmcounter29h", 0xC9D>;
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def: SysReg<"hpmcounter30h", 0xC9E>;
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def: SysReg<"hpmcounter31h", 0xC9F>;
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}
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//===--------------------------
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// Supervisor Trap Setup
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//===--------------------------
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def : SysReg<"sstatus", 0x100>;
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def : SysReg<"sedeleg", 0x102>;
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def : SysReg<"sideleg", 0x103>;
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def : SysReg<"sie", 0x104>;
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def : SysReg<"stvec", 0x105>;
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def : SysReg<"scounteren", 0x106>;
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//===--------------------------
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// Supervisor Trap Handling
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//===--------------------------
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def : SysReg<"sscratch", 0x140>;
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def : SysReg<"sepc", 0x141>;
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def : SysReg<"scause", 0x142>;
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def : SysReg<"stval", 0x143>;
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def : SysReg<"sip", 0x144>;
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//===-------------------------------------
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// Supervisor Protection and Translation
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//===-------------------------------------
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def : SysReg<"satp", 0x180>;
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//===-----------------------------
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// Machine Information Registers
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//===-----------------------------
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def : SysReg<"mvendorid", 0xF11>;
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def : SysReg<"marchid", 0xF12>;
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def : SysReg<"mimpid", 0xF13>;
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def : SysReg<"mhartid", 0xF14>;
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//===-----------------------------
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// Machine Trap Setup
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//===-----------------------------
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def : SysReg<"mstatus", 0x300>;
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def : SysReg<"misa", 0x301>;
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def : SysReg<"medeleg", 0x302>;
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def : SysReg<"mideleg", 0x303>;
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def : SysReg<"mie", 0x304>;
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def : SysReg<"mtvec", 0x305>;
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def : SysReg<"mcounteren", 0x306>;
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//===-----------------------------
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// Machine Trap Handling
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//===-----------------------------
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def : SysReg<"mscratch", 0x340>;
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def : SysReg<"mepc", 0x341>;
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def : SysReg<"mcause", 0x342>;
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def : SysReg<"mtval", 0x343>;
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def : SysReg<"mip", 0x344>;
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//===----------------------------------
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// Machine Protection and Translation
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//===----------------------------------
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def : SysReg<"pmpcfg0", 0x3A0>;
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def : SysReg<"pmpcfg2", 0x3A2>;
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let isRV32Only = 1 in {
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def : SysReg<"pmpcfg1", 0x3A1>;
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def : SysReg<"pmpcfg3", 0x3A3>;
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}
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def : SysReg<"pmpaddr0", 0x3B0>;
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def : SysReg<"pmpaddr1", 0x3B1>;
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def : SysReg<"pmpaddr2", 0x3B2>;
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def : SysReg<"pmpaddr3", 0x3B3>;
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def : SysReg<"pmpaddr4", 0x3B4>;
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def : SysReg<"pmpaddr5", 0x3B5>;
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def : SysReg<"pmpaddr6", 0x3B6>;
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def : SysReg<"pmpaddr7", 0x3B7>;
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def : SysReg<"pmpaddr8", 0x3B8>;
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def : SysReg<"pmpaddr9", 0x3B9>;
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def : SysReg<"pmpaddr10", 0x3BA>;
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def : SysReg<"pmpaddr11", 0x3BB>;
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def : SysReg<"pmpaddr12", 0x3BC>;
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def : SysReg<"pmpaddr13", 0x3BD>;
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def : SysReg<"pmpaddr14", 0x3BE>;
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def : SysReg<"pmpaddr15", 0x3BF>;
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//===--------------------------
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// Machine Counter and Timers
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//===--------------------------
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def : SysReg<"mcycle", 0xB00>;
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def : SysReg<"minstret", 0xB02>;
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def : SysReg<"mhpmcounter3", 0xB03>;
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def : SysReg<"mhpmcounter4", 0xB04>;
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def : SysReg<"mhpmcounter5", 0xB05>;
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def : SysReg<"mhpmcounter6", 0xB06>;
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def : SysReg<"mhpmcounter7", 0xB07>;
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def : SysReg<"mhpmcounter8", 0xB08>;
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def : SysReg<"mhpmcounter9", 0xB09>;
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def : SysReg<"mhpmcounter10", 0xB0A>;
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def : SysReg<"mhpmcounter11", 0xB0B>;
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def : SysReg<"mhpmcounter12", 0xB0C>;
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def : SysReg<"mhpmcounter13", 0xB0D>;
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def : SysReg<"mhpmcounter14", 0xB0E>;
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def : SysReg<"mhpmcounter15", 0xB0F>;
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def : SysReg<"mhpmcounter16", 0xB10>;
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def : SysReg<"mhpmcounter17", 0xB11>;
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def : SysReg<"mhpmcounter18", 0xB12>;
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def : SysReg<"mhpmcounter19", 0xB13>;
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def : SysReg<"mhpmcounter20", 0xB14>;
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def : SysReg<"mhpmcounter21", 0xB15>;
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def : SysReg<"mhpmcounter22", 0xB16>;
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def : SysReg<"mhpmcounter23", 0xB17>;
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def : SysReg<"mhpmcounter24", 0xB18>;
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def : SysReg<"mhpmcounter25", 0xB19>;
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def : SysReg<"mhpmcounter26", 0xB1A>;
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def : SysReg<"mhpmcounter27", 0xB1B>;
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def : SysReg<"mhpmcounter28", 0xB1C>;
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def : SysReg<"mhpmcounter29", 0xB1D>;
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def : SysReg<"mhpmcounter30", 0xB1E>;
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def : SysReg<"mhpmcounter31", 0xB1F>;
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let isRV32Only = 1 in {
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def: SysReg<"mcycleh", 0xB80>;
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def: SysReg<"minstreth", 0xB82>;
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def: SysReg<"mhpmcounter3h", 0xB83>;
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def: SysReg<"mhpmcounter4h", 0xB84>;
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def: SysReg<"mhpmcounter5h", 0xB85>;
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def: SysReg<"mhpmcounter6h", 0xB86>;
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def: SysReg<"mhpmcounter7h", 0xB87>;
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def: SysReg<"mhpmcounter8h", 0xB88>;
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def: SysReg<"mhpmcounter9h", 0xB89>;
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def: SysReg<"mhpmcounter10h", 0xB8A>;
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def: SysReg<"mhpmcounter11h", 0xB8B>;
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def: SysReg<"mhpmcounter12h", 0xB8C>;
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def: SysReg<"mhpmcounter13h", 0xB8D>;
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def: SysReg<"mhpmcounter14h", 0xB8E>;
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def: SysReg<"mhpmcounter15h", 0xB8F>;
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def: SysReg<"mhpmcounter16h", 0xB90>;
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def: SysReg<"mhpmcounter17h", 0xB91>;
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def: SysReg<"mhpmcounter18h", 0xB92>;
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def: SysReg<"mhpmcounter19h", 0xB93>;
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def: SysReg<"mhpmcounter20h", 0xB94>;
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def: SysReg<"mhpmcounter21h", 0xB95>;
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def: SysReg<"mhpmcounter22h", 0xB96>;
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def: SysReg<"mhpmcounter23h", 0xB97>;
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def: SysReg<"mhpmcounter24h", 0xB98>;
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def: SysReg<"mhpmcounter25h", 0xB99>;
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def: SysReg<"mhpmcounter26h", 0xB9A>;
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def: SysReg<"mhpmcounter27h", 0xB9B>;
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def: SysReg<"mhpmcounter28h", 0xB9C>;
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def: SysReg<"mhpmcounter29h", 0xB9D>;
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def: SysReg<"mhpmcounter30h", 0xB9E>;
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def: SysReg<"mhpmcounter31h", 0xB9F>;
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}
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//===--------------------------
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// Machine Counter Setup
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//===--------------------------
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def : SysReg<"mhpmevent3", 0x323>;
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def : SysReg<"mhpmevent4", 0x324>;
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def : SysReg<"mhpmevent5", 0x325>;
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def : SysReg<"mhpmevent6", 0x326>;
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def : SysReg<"mhpmevent7", 0x327>;
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def : SysReg<"mhpmevent8", 0x328>;
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def : SysReg<"mhpmevent9", 0x329>;
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def : SysReg<"mhpmevent10", 0x32A>;
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def : SysReg<"mhpmevent11", 0x32B>;
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def : SysReg<"mhpmevent12", 0x32C>;
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def : SysReg<"mhpmevent13", 0x32D>;
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def : SysReg<"mhpmevent14", 0x32E>;
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def : SysReg<"mhpmevent15", 0x32F>;
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def : SysReg<"mhpmevent16", 0x330>;
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def : SysReg<"mhpmevent17", 0x331>;
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def : SysReg<"mhpmevent18", 0x332>;
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def : SysReg<"mhpmevent19", 0x333>;
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def : SysReg<"mhpmevent20", 0x334>;
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def : SysReg<"mhpmevent21", 0x335>;
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def : SysReg<"mhpmevent22", 0x336>;
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def : SysReg<"mhpmevent23", 0x337>;
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def : SysReg<"mhpmevent24", 0x338>;
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def : SysReg<"mhpmevent25", 0x339>;
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def : SysReg<"mhpmevent26", 0x33A>;
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def : SysReg<"mhpmevent27", 0x33B>;
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def : SysReg<"mhpmevent28", 0x33C>;
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def : SysReg<"mhpmevent29", 0x33D>;
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def : SysReg<"mhpmevent30", 0x33E>;
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def : SysReg<"mhpmevent31", 0x33F>;
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//===-----------------------------------------------
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// Debug/ Trace Registers (shared with Debug Mode)
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//===-----------------------------------------------
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def : SysReg<"tselect", 0x7A0>;
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def : SysReg<"tdata1", 0x7A1>;
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def : SysReg<"tdata2", 0x7A2>;
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def : SysReg<"tdata3", 0x7A3>;
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//===-----------------------------------------------
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// Debug Mode Registers
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//===-----------------------------------------------
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def : SysReg<"dcsr", 0x7B0>;
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def : SysReg<"dpc", 0x7B1>;
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def : SysReg<"dscratch", 0x7B2>;
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