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llvm-project/llvm/test/CodeGen
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Jon Roelofs b046eb19b8 [AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0 
https://godbolt.org/z/h8ejrG4hb

rdar://83597585

Differential Revision: https://reviews.llvm.org/D111856
2021-10-20 12:11:52 -07:00
..
AArch64
[AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0
2021-10-20 12:11:52 -07:00
AMDGPU
[AMDGPU] MachineLICM cannot hoist VALU
2021-10-20 11:47:24 -07:00
ARC
…
ARM
[ARM] Fix MOVCC peephole to not use an incorrect register class
2021-10-15 10:54:26 +01:00
AVR
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
BPF
BPF: set .BTF and .BTF.ext section alignment to 4
2021-10-19 16:26:01 -07:00
Generic
[AIX] Disable tests failing due to lack of .loc and .file directive support
2021-10-08 11:55:12 -04:00
Hexagon
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Inputs
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Lanai
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M68k
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Mips
[Mips] Add glue between CopyFromReg, CopyToReg and RDHWR nodes for TLS
2021-10-18 15:10:20 +01:00
MIR
DebugInfo: Use clang's preferred names for integer types
2021-10-06 16:02:34 -07:00
MSP430
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NVPTX
[NVPTX] Add a late SROA pass which allows optimizing away more allocas.
2021-10-19 16:18:28 -07:00
PowerPC
[NewPM][test] Avoid using -enable-new-pm=1 since -passes implies new PM
2021-10-20 15:16:17 +02:00
RISCV
[RISCV][WebAssembly][TargetLowering] Allow expandCTLZ/expandCTTZ to rely on CTPOP expansion for vectors.
2021-10-20 07:46:41 -07:00
SPARC
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SystemZ
[SystemZ] Handle huge immediates in SystemZInstrInfo::loadImmediate().
2021-10-15 19:08:45 +02:00
Thumb
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
Thumb2
[ARM] Introduce a MQPRCopy
2021-10-07 12:52:12 +01:00
VE
[VE][Test] Make Scalar/va_arg test generic
2021-10-08 08:07:51 +02:00
WebAssembly
[WebAssembly] Add prototype relaxed float min max instructions
2021-10-20 09:41:51 -07:00
WinCFGuard
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WinEH
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X86
[x86] add special-case lowering for usubsat for pre-SSE4
2021-10-19 17:13:16 -04:00
XCore
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