4ea121c904
There are a few issues with the code we generate for atomic operations and the way we generate it: - Hard coded CR0 for compares - Order of operands for compares not conducive to emitting compare-immediate or for CSE of compares - Missing MachineMemOperand for st[bhwd]cx intrinsics - Missing intrinsic properties for the same - Unnecessary blocks with store conditional instructions to clear reservation (which ends up hindering performance) - Move from CR instructions just to compare the result of a store conditional with zero (even though it is a record-form) This patch aims to resolve all of those issues. Differential revision: https://reviews.llvm.org/D134783
20 lines
630 B
LLVM
20 lines
630 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
|
|
|
|
define void @test(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; PPC64LE-LABEL: test:
|
|
; PPC64LE: # %bb.0:
|
|
; PPC64LE-NEXT: clrlwi 4, 4, 24
|
|
; PPC64LE-NEXT: .LBB0_1:
|
|
; PPC64LE-NEXT: lbarx 6, 0, 3
|
|
; PPC64LE-NEXT: cmpw 6, 4
|
|
; PPC64LE-NEXT: bnelr 0
|
|
; PPC64LE-NEXT: # %bb.2:
|
|
; PPC64LE-NEXT: stbcx. 5, 0, 3
|
|
; PPC64LE-NEXT: bne 0, .LBB0_1
|
|
; PPC64LE-NEXT: # %bb.3:
|
|
; PPC64LE-NEXT: blr
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
|
|
ret void
|
|
}
|