Matt Arsenault ccf28ea800 AMDGPU: Move codegen test out of MIR test directory ...

This is testing an actual pass, not the MIR parser/printer.

2021-06-07 14:26:48 -04:00

..

custom-pseudo-source-values.ll

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

expected-target-index-name.mir

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intrinsics.mir

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invalid-frame-index2.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-fixed-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-invalid-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index-no-stack.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-frame-index.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

invalid-target-index-operand.mir

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lit.local.cfg

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llc-target-cpu-attr-from-cmdline-ir.mir

Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""

2020-11-11 14:40:14 +00:00

llc-target-cpu-attr-from-cmdline.mir

Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""

2020-11-11 14:40:14 +00:00

load-store-opt-dlc.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

machine-function-info-after-pei.ll

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

machine-function-info-dynlds-align-invalid-case.mir

[amdgpu] Add codegen support for HIP dynamic shared memory.

2020-08-20 21:29:18 -04:00

machine-function-info-no-ir.mir

[AMDGPU] Serialize MFInfo::ScavengeFI

2021-05-07 11:15:25 +02:00

machine-function-info-register-parse-error1.mir

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machine-function-info-register-parse-error2.mir

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machine-function-info.ll

[AMDGPU] Lower kernel LDS into a sorted structure

2021-05-25 11:29:29 -07:00

mfi-frame-offset-reg-class.mir

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mfi-parse-error-frame-offset-reg.mir

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mfi-parse-error-scratch-rsrc-reg.mir

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mfi-parse-error-stack-ptr-offset-reg.mir

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mfi-scratch-rsrc-reg-reg-class.mir

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mfi-stack-ptr-offset-reg-class.mir

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mir-canon-multi.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

mircanon-memoperands.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

parse-order-reserved-regs.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

stack-id-assert.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

stack-id.mir

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subreg-def-is-not-ssa.mir

MIR: Infer not-SSA for subregister defs

2020-08-27 16:56:16 -04:00

syncscopes.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00

target-flags.mir

[AMDGPU] Fix offset for REL32_HI relocs

2020-09-02 10:55:55 +01:00

target-index-operands.mir

[AMDGPU] Use single cache policy operand

2021-03-15 13:00:59 -07:00