00c0c8c87d
On ppc64 linux , MachineLICM will hoist caller preserved registers, including TOC loads of the global variable address, out of loops. This is to enable this on AIX for both ppc64 and ppc32. Differential Revision: https://reviews.llvm.org/D99076
119 lines
4.8 KiB
LLVM
119 lines
4.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck -check-prefixes=CHECK,CHECKLX %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck -check-prefixes=CHECK,CHECKAIX32 %s
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; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
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; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
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; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler
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; to insert a save TOC to stack before the call and load into X2 to restore TOC
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; after. By communicating to Machine LICM that X2 is guaranteed to have the
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; same value before and after BCTRL_LDinto_toc, these instructions can be
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; hoisted out of bb.3.if.end to outside of the loop.
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; Pre Machine LICM MIR
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;
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;body:
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; bb.0.entry:
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; successors: %bb.2.if.then(0x40000000), %bb.3.if.end(0x40000000)
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; liveins: %x3
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;
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; %4 = COPY %x3
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; %5 = ADDIStocHA8 %x2, @ga
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; %6 = LDtocL @ga, killed %5 :: (load 8 from got)
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; %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
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; %8 = ADDIStocHA8 %x2, @gb
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; %9 = LDtocL @gb, killed %8 :: (load 8 from got)
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; %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb)
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; %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
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; %11 = CMPW killed %7, killed %10
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; BCC 44, killed %11, %bb.2.if.then
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; B %bb.3.if.end
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;
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; bb.2.if.then:
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; %1 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
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; ADJCALLSTACKDOWN 32, 0, implicit-def dead %r1, implicit %r1
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; %20 = COPY %x2
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; STD %20, 24, %x1 :: (store 8 into stack + 24)
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; %21 = EXTSW_32_64 %1
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; %x3 = COPY %21
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; %x12 = COPY %4
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; MTCTR8 %4, implicit-def %ctr8
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; BCTRL8_LDinto_toc 24, %x1, csr_ppc64_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3
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; ADJCALLSTACKUP 32, 0, implicit-def dead %r1, implicit %r1
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; %22 = COPY %x3
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; %x3 = COPY %22
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; BLR8 implicit %lr8, implicit %rm, implicit %x3
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;
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; bb.3.if.end:
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; successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000)
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;
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; %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
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; %12 = ADDI %2, 1
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; %13 = ADDIStocHA8 %x2, @ga
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; %14 = LDtocL @ga, killed %13 :: (load 8 from got)
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; STW killed %12, 0, %14 :: (volatile store 4 into @ga)
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; %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
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; %16 = ADDIStocHA8 %x2, @gb
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; %17 = LDtocL @gb, killed %16 :: (load 8 from got)
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; %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb)
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; %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
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; %19 = CMPW killed %15, killed %18
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; BCC 44, killed %19, %bb.2.if.then
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; B %bb.3.if.end
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@ga = external global i32, align 4
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@gb = external global i32, align 4
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define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECKLX: addis 4, 2, .LC0@toc@ha
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; CHECKLX-NEXT: addis 5, 2, .LC1@toc@ha
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; CHECKLX-NEXT: mr 12, 3
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; CHECKLX-NEXT: ld 4, .LC0@toc@l(4)
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; CHECKLX-NEXT: ld 5, .LC1@toc@l(5)
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; CHECKLX-NEXT: lwz 6, 0(4)
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; CHECKLX-NEXT: lwz 7, 0(5)
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; CHECKLX-NEXT: cmpw 6, 7
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; CHECKLX-NEXT: lwz 6, 0(4)
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; CHECKLX-NEXT: bgt 0, .LBB0_2
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; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha
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; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha
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; CHECKLX-NEXT: .p2align 5
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; CHECKLX-NEXT: .LBB0_1: # %if.end
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; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha
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; CHECKLX-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha
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; CHECKAIX: ld 5, L..C0(2)
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; CHECKAIX-NEXT: ld 6, L..C1(2)
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; CHECKAIX-NEXT: L..BB0_1: # %if.end
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; CHECKAIX-NOT: ld {{[0-9]+}}, L..C0(2)
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; CHECKAIX-NOT: ld {{[0-9]+}}, L..C1(2)
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; CHECKAIX32: lwz 5, L..C0(2)
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; CHECKAIX32-NEXT: lwz 6, L..C1(2)
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; CHECKAIX32-NEXT: L..BB0_1: # %if.end
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; CHECKAIX32-NOT: lwz 5, L..C0(2)
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; CHECKAIX32-NOT: lwz 6, L..C1(2)
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; CHECK: blr
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entry:
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%0 = load volatile i32, i32* @ga, align 4
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%1 = load volatile i32, i32* @gb, align 4
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%cmp1 = icmp sgt i32 %0, %1
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%2 = load volatile i32, i32* @ga, align 4
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %if.end, %entry
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%.lcssa = phi i32 [ %2, %entry ], [ %6, %if.end ]
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%call = tail call signext i32 %FP(i32 signext %.lcssa) #1
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ret i32 %call
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if.end: ; preds = %entry, %if.end
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%3 = phi i32 [ %6, %if.end ], [ %2, %entry ]
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%inc = add nsw i32 %3, 1
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store volatile i32 %inc, i32* @ga, align 4
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%4 = load volatile i32, i32* @ga, align 4
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%5 = load volatile i32, i32* @gb, align 4
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%cmp = icmp sgt i32 %4, %5
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%6 = load volatile i32, i32* @ga, align 4
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br i1 %cmp, label %if.then, label %if.end
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}
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