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llvm-project/llvm/test/CodeGen/RISCV
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Fraser Cormack a4729f7f88 [RISCV] Lower RVV vector SELECTs to VSELECTs 
This patch optimizes the code generation of vector-type SELECTs (LLVM
select instructions with scalar conditions) by custom-lowering to
VSELECTs (LLVM select instructions with vector conditions) by splatting
the condition to a vector. This avoids the default expansion path which
would either introduce control flow or fully scalarize.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104772
2021-06-24 10:12:51 +01:00
..
GlobalISel
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
intrinsics
[RISCV] Lower llvm.trap and llvm.debugtrap
2019-10-28 09:54:33 +00:00
rvv
[RISCV] Lower RVV vector SELECTs to VSELECTs
2021-06-24 10:12:51 +01:00
add-before-shl.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
add-imm.ll
[RISCV] Optimize addition with immediate
2021-04-26 13:26:17 +08:00
addc-adde-sube-subc.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
addcarry.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
addimm-mulimm.ll
[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
2020-07-10 18:33:12 -07:00
addrspacecast.ll
[RISCV] Assume no-op addrspacecasts by default
2020-12-18 21:03:37 +00:00
align.ll
…
alloca.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
alu8.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
alu16.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
alu32.ll
[RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffffffff).
2021-03-25 09:03:25 -07:00
alu64.ll
[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
2020-11-25 21:57:48 -08:00
analyze-branch.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
arith-with-overflow.ll
[TargetLowering] Simplify expansion of S{ADD,SUB}O
2019-09-30 07:58:50 +00:00
atomic-cmpxchg-flag.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
atomic-cmpxchg.ll
[AtomicExpand] Merge cmpxchg success and failure ordering when appropriate.
2021-06-03 11:34:35 -07:00
atomic-fence.ll
…
atomic-load-store.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
atomic-rmw.ll
[RISCV] Copy isUnneededShiftMask from X86.
2021-01-27 20:46:10 -08:00
atomic-signext.ll
[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics
2021-05-20 20:34:23 +01:00
attributes.ll
[RISCV] Update the version number to v0.10 for vector.
2021-01-30 07:20:05 +08:00
blockaddress.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
branch-relaxation.ll
[RISCV] Indirect branch generation in position independent code
2020-08-17 13:09:26 +01:00
branch.ll
[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
2021-03-15 11:32:43 -07:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
byval.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
callee-saved-fpr32s.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
callee-saved-fpr64s.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
callee-saved-gprs.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-half.ll
[RISCV] Improve 64-bit integer constant materialization for more cases.
2021-04-02 10:18:08 -07:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32d.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-lp64.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-rv32f-ilp32.ll
[RISCV][NFC] Regenerate Calling Convention Tests
2021-01-14 22:35:17 +00:00
calling-conv-sext-zext.ll
[RISCV] Don't print zext.b alias.
2021-01-05 10:41:08 -08:00
calls.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
cmp-bool.ll
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
2020-07-15 07:34:22 +00:00
codemodel-lowering.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
compress-float.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
compress-inline-asm.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
compress.ll
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
2020-12-04 10:34:12 -08:00
copy-frameindex.mir
[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
2020-11-03 03:55:47 +00:00
copysign-casts.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
disable-tail-calls.ll
…
disjoint.ll
[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
2019-11-05 09:39:06 +00:00
div.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
double-arith.ll
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
double-bitmanip-dagcombines.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
double-br-fcmp.ll
[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
2021-01-19 11:21:48 -08:00
double-calling-conv.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-convert.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
double-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
double-frem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
double-intrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
double-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
double-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
double-previous-failure.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
double-select-fcmp.ll
[RISCV] Optimize select_cc after fp compare expansion
2021-01-14 13:41:40 -08:00
double-stack-spill-restore.ll
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
2021-01-25 16:37:21 -08:00
dwarf-eh.ll
[RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
2019-07-17 14:04:48 +00:00
elf-preemption.ll
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-11 11:29:45 -07:00
exception-pointer-register.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fastcc-float.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fastcc-int.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fixups-diff.ll
test: clean up some of the RISCV tests (NFC)
2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll
test: clean up some of the RISCV tests (NFC)
2021-06-17 09:51:09 -07:00
float-arith.ll
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
float-bit-preserving-dagcombines.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll
[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
2021-01-19 11:21:48 -08:00
float-convert.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
float-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
float-frem.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
float-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
float-intrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
float-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
float-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
float-select-fcmp.ll
[RISCV] Optimize select_cc after fp compare expansion
2021-01-14 13:41:40 -08:00
flt-rounds.ll
…
fold-addi-loadstore.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
fp16-promote.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
fp128.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
fp-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
fpenv.ll
[RISCV] Custom lowering of SET_ROUNDING
2021-04-22 15:04:55 +07:00
frame-info.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
frame.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
frameaddr-returnaddr.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
get-register-invalid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
get-register-noreserve.ll
[RISCV] Implement the TargetLowering::getRegisterByName hook
2019-11-04 11:23:54 +00:00
get-register-reserve.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
get-setcc-result-type.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
ghccc-rv32.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
ghccc-rv64.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
half-arith.ll
[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
2020-12-02 21:13:42 -08:00
half-bitmanip-dagcombines.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
half-br-fcmp.ll
[RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
2021-01-19 11:21:48 -08:00
half-convert.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
half-fcmp.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
half-imm.ll
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
half-intrinsics.ll
[RISCV] Add f16 to isFMAFasterThanFMulAndFAdd now that the Zfh extension is supported
2020-12-02 20:31:43 -08:00
half-isnan.ll
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
half-mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
half-select-fcmp.ll
[RISCV] Optimize select_cc after fp compare expansion
2021-01-14 13:41:40 -08:00
hoist-global-addr-base.ll
[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
2021-03-15 11:32:43 -07:00
i32-icmp.ll
[RISCV] Optimize seteq/setne pattern expansions for better code size
2020-02-11 22:45:15 +08:00
imm-cse.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
imm.ll
[RISCV] Improve 64-bit integer constant materialization for more cases.
2021-04-02 10:18:08 -07:00
indirectbr.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
init-array.ll
…
inline-asm-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-clobbers.ll
[RISCV] Add support for lowering floating point inlineasm clobbers
2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
inline-asm-f-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-f-constraint-f.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm.ll
[MC][RISCV] Set UseIntegratedAssembler to true
2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr-callee.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
interrupt-attr-invalid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr-nocall.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
interrupt-attr-ret-error.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
jumptable.ll
[CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt.
2021-06-23 15:38:11 -07:00
large-stack.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
legalize-fneg.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll
[RISCV] Switch to the Machine Scheduler
2019-09-17 11:15:35 +00:00
machineoutliner.mir
[RISCV] Enable the machine outliner for RISC-V
2019-12-19 16:41:53 +00:00
mattr-invalid-combination.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
mem64.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
mem.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
mir-target-flags.ll
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
2020-12-05 14:54:37 -08:00
module-target-abi2.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
module-target-abi.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
mul.ll
[RISCV] Add custom type legalization to form MULHSU when possible.
2021-04-01 10:15:55 -07:00
musttail-call.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
neg-abs.ll
[RISCV][NFC] Increase test coverage of Zbt extension
2021-01-18 17:30:35 +00:00
nomerge.ll
Add NoMerge MIFlag to avoid MIR branch folding
2020-05-29 12:31:06 -07:00
option-nopic.ll
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
option-norelax.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
option-norvc.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
option-pic.ll
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
option-relax.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
option-rvc.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
out-of-reach-emergency-slot.mir
[RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer
2021-01-23 09:10:03 +00:00
patchable-function-entry.ll
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
2021-05-29 15:11:37 +01:00
pic-models.ll
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
pr40333.ll
…
prefetch.ll
…
readcyclecounter.ll
…
rem.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
remat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
reserved-reg-errors.ll
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
reserved-regs.ll
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
rotl-rotr.ll
…
rv32e.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
rv32i-rv64i-float-double.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv32i-rv64i-half.ll
[RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.
2021-04-01 12:41:57 -07:00
rv32zba.ll
[RISCV] Optimize add-mul in the zba extension with SH*ADD
2021-06-19 14:33:27 +08:00
rv32zbb-intrinsic.ll
Recommit "[RISCV] Add IR intrinsic for Zbb extension"
2021-04-02 11:50:19 -07:00
rv32zbb-zbp.ll
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
2021-04-29 09:43:51 -07:00
rv32zbb.ll
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
2021-03-22 19:17:04 -07:00
rv32zbc-intrinsic.ll
[RISCV] Add IR intrinsics for Zbc extension
2021-04-02 12:09:13 -07:00
rv32zbe-intrinsic.ll
[RISCV] [1/2] Add IR intrinsic for Zbe extension
2021-04-25 19:14:34 -07:00
rv32zbp-intrinsic.ll
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
2021-04-25 21:54:06 -07:00
rv32zbp.ll
[RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp.
2021-06-07 10:31:51 -07:00
rv32zbr.ll
[RISCV] Add IR intrinsic for Zbr extension
2021-04-02 10:58:45 -07:00
rv32zbs.ll
[RISCV] Optimize bitwise and with constant for the Zbs extension
2021-06-08 07:26:00 +08:00
rv32zbt.ll
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
2021-04-29 09:43:51 -07:00
rv64-large-stack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64d-double-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64f-float-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64f-half-convert.ll
[RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg.
2020-12-04 18:40:02 -08:00
rv64i-complex-float.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-demanded-bits.ll
[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
2020-10-29 14:52:53 -07:00
rv64i-double-softfloat.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
rv64i-exhaustive-w-insts.ll
[RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3.
2021-03-25 23:31:01 -07:00
rv64i-single-softfloat.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64
2021-03-20 14:55:46 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.
2021-02-22 14:56:22 -08:00
rv64m-w-insts-legalization.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
rv64zba.ll
[RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.
2021-06-19 12:10:42 -07:00
rv64zbb-intrinsic.ll
[RISCV] Use gorciw for i32 orc.b intrinsic when Zbp is enabled.
2021-04-04 17:14:28 -07:00
rv64zbb-zbp.ll
[RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64.
2021-04-11 13:59:51 -07:00
rv64zbb.ll
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
2021-06-10 19:06:45 -07:00
rv64zbc-intrinsic.ll
[RISCV] Add IR intrinsics for Zbc extension
2021-04-02 12:09:13 -07:00
rv64zbe-intrinsic.ll
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
2021-04-25 21:54:06 -07:00
rv64zbp-intrinsic.ll
[RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
2021-04-25 21:54:06 -07:00
rv64zbp.ll
[RISCV] Lower i8/i16 bswap/bitreverse to grevi/greviw with Zbp.
2021-06-07 10:31:51 -07:00
rv64zbr.ll
[RISCV] Add IR intrinsic for Zbr extension
2021-04-02 10:58:45 -07:00
rv64zbs.ll
[RISCV] Optimize bitwise and with constant for the Zbs extension
2021-06-08 07:26:00 +08:00
rv64zbt.ll
[RISCV] Rename Zb* extension tests to use lower case 'Z' in file names.
2021-03-22 19:17:04 -07:00
sadd_sat_plus.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
sadd_sat.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
saverestore.ll
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
scalable-vector-struct.ll
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
sdata-limit-0.ll
…
sdata-limit-4.ll
…
sdata-limit-8.ll
…
sdata-local-sym.ll
…
select-and.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-bare.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-binop-identity.ll
[RISCV] Teach DAG combine to fold (and (select_cc lhs, rhs, cc, -1, c), x) -> (select_cc lhs, rhs, cc, x, (and, x, c))
2021-04-29 09:43:51 -07:00
select-cc.ll
[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.
2021-03-12 11:50:10 -08:00
select-const.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
select-optimize-multiple.ll
[RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.
2021-01-22 14:51:22 -08:00
select-optimize-multiple.mir
[RISCV][NFC] Increase test coverage of Zbt extension
2021-01-18 17:30:35 +00:00
select-or.ll
Recommit "[RISCV] Legalize select when Zbt extension available"
2021-01-21 12:07:44 -08:00
setcc-logic.ll
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
2021-01-25 16:37:21 -08:00
sext-zext-trunc.ll
[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper
2021-01-25 16:37:21 -08:00
shadowcallstack.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
shift-masked-shamt.ll
[RISCV] Copy isUnneededShiftMask from X86.
2021-01-27 20:46:10 -08:00
shifts.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
shrinkwrap.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
spill-fpr-scalar.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
split-offsets.ll
[RISCV] Fix wrong CFI directives
2019-11-14 18:29:50 +00:00
split-sp-adjust.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
srem-lkk.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
srem-seteq-illegal-types.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
srem-vector-lkk.ll
[RISCV] Improve 64-bit integer materialization for some cases.
2021-04-01 09:12:52 -07:00
ssub_sat_plus.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
ssub_sat.ll
[RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
2021-04-07 13:47:17 -07:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
2021-01-15 11:14:14 -08:00
stack-realignment.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
stack-slot-size.ll
[RISCV] Fix stack slot for argument types (Bug 49500)
2021-04-29 09:10:48 +01:00
stack-store-check.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
subtarget-features-std-ext.ll
[RISCV] Support ABI checking with per function target-features
2020-01-22 08:12:28 -08:00
tail-calls.ll
OpaquePtr: Bulk update tests to use typed sret
2020-11-20 17:58:26 -05:00
target-abi-invalid.ll
…
target-abi-valid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
thread-pointer.ll
[RISCV] Support llvm.thread.pointer
2020-03-27 17:30:12 -07:00
tls-models.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
uadd_sat_plus.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
uadd_sat.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
umulo-128-legalisation-lowering.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
urem-lkk.ll
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.
2021-02-11 09:43:13 -08:00
urem-seteq-illegal-types.ll
[RISCV][NFC] Add a single space after comma for VType
2021-06-09 11:18:22 +08:00
urem-vector-lkk.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
usub_sat_plus.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
usub_sat.ll
[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.
2021-03-16 07:44:06 -07:00
vararg.ll
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
vec3-setcc-crash.ll
[RISCV] Fix a codegen crash in getSetCCResultType
2021-01-27 10:22:54 +00:00
vector-abi.ll
[RISCV] Fix stack slot for argument types (Bug 49500)
2021-04-29 09:10:48 +01:00
verify-instr.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
wide-mem.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
xaluo.ll
[RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation
2021-03-27 15:37:18 -07:00
zext-with-load-is-free.ll
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
2020-12-30 15:28:11 -08:00
zfh-imm.ll
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00