e9bcd2bf67
Referring to RISC-V, adding an MI level pass to optimize *W instructions for LoongArch. First it removes unneeded sext(addi.w rd, rs, 0) instructions. Either because the sign extended bits aren't consumed or because the input was already sign extended by an earlier instruction. Then: 1. Unless explicit disabled or the target prefers instructions with W suffix, it removes the -w suffix from opw instructions whenever all users are dependent only on the lower word of the result of the instruction. The cases handled are: * addi.w because it helps reduce test differences between LA32 and LA64 w/o being a pessimization. 2. Or if explicit enabled or the target prefers instructions with W suffix, it adds the W suffix to the instruction whenever all users are dependent only on the lower word of the result of the instruction. The cases handled are: * add.d/addi.d/sub.d/mul.d. * slli.d with imm < 32. * ld.d/ld.wu.
549 lines
19 KiB
C++
549 lines
19 KiB
C++
//=- LoongArchInstrInfo.cpp - LoongArch Instruction Information -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the LoongArch implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchInstrInfo.h"
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#include "LoongArch.h"
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#include "LoongArchMachineFunctionInfo.h"
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#include "LoongArchRegisterInfo.h"
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#include "MCTargetDesc/LoongArchMCTargetDesc.h"
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#include "MCTargetDesc/LoongArchMatInt.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/MCInstBuilder.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "LoongArchGenInstrInfo.inc"
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LoongArchInstrInfo::LoongArchInstrInfo(LoongArchSubtarget &STI)
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: LoongArchGenInstrInfo(LoongArch::ADJCALLSTACKDOWN,
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LoongArch::ADJCALLSTACKUP),
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STI(STI) {}
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MCInst LoongArchInstrInfo::getNop() const {
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return MCInstBuilder(LoongArch::ANDI)
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.addReg(LoongArch::R0)
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.addReg(LoongArch::R0)
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.addImm(0);
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}
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void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, MCRegister DstReg,
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MCRegister SrcReg, bool KillSrc) const {
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if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addReg(LoongArch::R0);
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return;
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}
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// VR->VR copies.
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if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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return;
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}
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// XR->XR copies.
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if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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return;
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}
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// GPR->CFR copy.
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if (LoongArch::CFRRegClass.contains(DstReg) &&
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LoongArch::GPRRegClass.contains(SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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// CFR->GPR copy.
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if (LoongArch::GPRRegClass.contains(DstReg) &&
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LoongArch::CFRRegClass.contains(SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::MOVCF2GR), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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// CFR->CFR copy.
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if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, MBBI, DL, get(LoongArch::PseudoCopyCFR), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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// FPR->FPR copies.
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unsigned Opc;
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if (LoongArch::FPR32RegClass.contains(DstReg, SrcReg)) {
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Opc = LoongArch::FMOV_S;
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} else if (LoongArch::FPR64RegClass.contains(DstReg, SrcReg)) {
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Opc = LoongArch::FMOV_D;
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} else if (LoongArch::GPRRegClass.contains(DstReg) &&
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LoongArch::FPR32RegClass.contains(SrcReg)) {
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// FPR32 -> GPR copies
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Opc = LoongArch::MOVFR2GR_S;
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} else if (LoongArch::GPRRegClass.contains(DstReg) &&
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LoongArch::FPR64RegClass.contains(SrcReg)) {
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// FPR64 -> GPR copies
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Opc = LoongArch::MOVFR2GR_D;
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} else {
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// TODO: support other copies.
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void LoongArchInstrInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
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bool IsKill, int FI, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg) const {
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MachineFunction *MF = MBB.getParent();
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MachineFrameInfo &MFI = MF->getFrameInfo();
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unsigned Opcode;
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if (LoongArch::GPRRegClass.hasSubClassEq(RC))
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Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
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? LoongArch::ST_W
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: LoongArch::ST_D;
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else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::FST_S;
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else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::FST_D;
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else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::VST;
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else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::XVST;
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else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
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Opcode = LoongArch::PseudoST_CFR;
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else
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llvm_unreachable("Can't store this register to stack slot");
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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BuildMI(MBB, I, DebugLoc(), get(Opcode))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void LoongArchInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DstReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const {
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MachineFunction *MF = MBB.getParent();
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MachineFrameInfo &MFI = MF->getFrameInfo();
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unsigned Opcode;
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if (LoongArch::GPRRegClass.hasSubClassEq(RC))
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Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
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? LoongArch::LD_W
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: LoongArch::LD_D;
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else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::FLD_S;
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else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::FLD_D;
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else if (LoongArch::LSX128RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::VLD;
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else if (LoongArch::LASX256RegClass.hasSubClassEq(RC))
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Opcode = LoongArch::XVLD;
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else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
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Opcode = LoongArch::PseudoLD_CFR;
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else
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llvm_unreachable("Can't load this register from stack slot");
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void LoongArchInstrInfo::movImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DstReg,
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uint64_t Val, MachineInstr::MIFlag Flag) const {
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Register SrcReg = LoongArch::R0;
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if (!STI.is64Bit() && !isInt<32>(Val))
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report_fatal_error("Should only materialize 32-bit constants for LA32");
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auto Seq = LoongArchMatInt::generateInstSeq(Val);
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assert(!Seq.empty());
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for (auto &Inst : Seq) {
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switch (Inst.Opc) {
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case LoongArch::LU12I_W:
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BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
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.addImm(Inst.Imm)
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.setMIFlag(Flag);
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break;
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case LoongArch::ADDI_W:
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case LoongArch::ORI:
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case LoongArch::LU32I_D: // "rj" is needed due to InstrInfo pattern
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case LoongArch::LU52I_D:
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BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg)
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.addReg(SrcReg, RegState::Kill)
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.addImm(Inst.Imm)
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.setMIFlag(Flag);
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break;
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default:
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assert(false && "Unknown insn emitted by LoongArchMatInt");
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}
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// Only the first instruction has $zero as its source.
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SrcReg = DstReg;
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}
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}
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unsigned LoongArchInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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unsigned Opcode = MI.getOpcode();
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if (Opcode == TargetOpcode::INLINEASM ||
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Opcode == TargetOpcode::INLINEASM_BR) {
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const MachineFunction *MF = MI.getParent()->getParent();
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const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
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return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
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}
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return MI.getDesc().getSize();
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}
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MachineBasicBlock *
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LoongArchInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
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assert(MI.getDesc().isBranch() && "Unexpected opcode!");
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// The branch target is always the last operand.
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return MI.getOperand(MI.getNumExplicitOperands() - 1).getMBB();
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}
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static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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// Block ends with fall-through condbranch.
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assert(LastInst.getDesc().isConditionalBranch() &&
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"Unknown conditional branch");
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int NumOp = LastInst.getNumExplicitOperands();
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Target = LastInst.getOperand(NumOp - 1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
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for (int i = 0; i < NumOp - 1; i++)
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Cond.push_back(LastInst.getOperand(i));
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}
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bool LoongArchInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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TBB = FBB = nullptr;
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Cond.clear();
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end() || !isUnpredicatedTerminator(*I))
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return false;
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// Count the number of terminators and find the first unconditional or
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// indirect branch.
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MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
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int NumTerminators = 0;
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for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
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J++) {
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NumTerminators++;
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if (J->getDesc().isUnconditionalBranch() ||
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J->getDesc().isIndirectBranch()) {
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FirstUncondOrIndirectBr = J.getReverse();
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}
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}
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// If AllowModify is true, we can erase any terminators after
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// FirstUncondOrIndirectBR.
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if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
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while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
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std::next(FirstUncondOrIndirectBr)->eraseFromParent();
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NumTerminators--;
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}
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I = FirstUncondOrIndirectBr;
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}
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// Handle a single unconditional branch.
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if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
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TBB = getBranchDestBlock(*I);
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return false;
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}
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// Handle a single conditional branch.
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if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
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parseCondBranch(*I, TBB, Cond);
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return false;
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}
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// Handle a conditional branch followed by an unconditional branch.
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if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
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I->getDesc().isUnconditionalBranch()) {
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parseCondBranch(*std::prev(I), TBB, Cond);
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FBB = getBranchDestBlock(*I);
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return false;
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}
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// Otherwise, we can't handle this.
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return true;
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}
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bool LoongArchInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
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int64_t BrOffset) const {
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switch (BranchOp) {
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default:
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llvm_unreachable("Unknown branch instruction!");
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case LoongArch::BEQ:
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case LoongArch::BNE:
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case LoongArch::BLT:
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case LoongArch::BGE:
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case LoongArch::BLTU:
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case LoongArch::BGEU:
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return isInt<18>(BrOffset);
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case LoongArch::BEQZ:
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case LoongArch::BNEZ:
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case LoongArch::BCEQZ:
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case LoongArch::BCNEZ:
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return isInt<23>(BrOffset);
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case LoongArch::B:
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case LoongArch::PseudoBR:
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return isInt<28>(BrOffset);
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}
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}
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unsigned LoongArchInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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if (BytesRemoved)
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*BytesRemoved = 0;
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return 0;
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if (!I->getDesc().isBranch())
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return 0;
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// Remove the branch.
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (!I->getDesc().isConditionalBranch())
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return 1;
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// Remove the branch.
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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I->eraseFromParent();
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return 2;
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}
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// Inserts a branch into the end of the specific MachineBasicBlock, returning
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// the number of instructions inserted.
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unsigned LoongArchInstrInfo::insertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
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if (BytesAdded)
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*BytesAdded = 0;
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// Shouldn't be a fall through.
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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assert(Cond.size() <= 3 && Cond.size() != 1 &&
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"LoongArch branch conditions have at most two components!");
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// Unconditional branch.
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if (Cond.empty()) {
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MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 1;
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}
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// Either a one or two-way conditional branch.
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
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for (unsigned i = 1; i < Cond.size(); ++i)
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MIB.add(Cond[i]);
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MIB.addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(*MIB);
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// One-way conditional branch.
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if (!FBB)
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return 1;
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// Two-way conditional branch.
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MachineInstr &MI = *BuildMI(&MBB, DL, get(LoongArch::PseudoBR)).addMBB(FBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 2;
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}
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void LoongArchInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &DestBB,
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MachineBasicBlock &RestoreBB,
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const DebugLoc &DL,
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int64_t BrOffset,
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RegScavenger *RS) const {
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assert(RS && "RegScavenger required for long branching");
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assert(MBB.empty() &&
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"new block should be inserted for expanding unconditional branch");
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assert(MBB.pred_size() == 1);
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MachineFunction *MF = MBB.getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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LoongArchMachineFunctionInfo *LAFI =
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MF->getInfo<LoongArchMachineFunctionInfo>();
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if (!isInt<32>(BrOffset))
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report_fatal_error(
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"Branch offsets outside of the signed 32-bit range not supported");
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Register ScratchReg = MRI.createVirtualRegister(&LoongArch::GPRRegClass);
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auto II = MBB.end();
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MachineInstr &PCALAU12I =
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*BuildMI(MBB, II, DL, get(LoongArch::PCALAU12I), ScratchReg)
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.addMBB(&DestBB, LoongArchII::MO_PCREL_HI);
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MachineInstr &ADDI =
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*BuildMI(MBB, II, DL,
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get(STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W),
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ScratchReg)
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.addReg(ScratchReg)
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.addMBB(&DestBB, LoongArchII::MO_PCREL_LO);
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BuildMI(MBB, II, DL, get(LoongArch::PseudoBRIND))
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.addReg(ScratchReg, RegState::Kill)
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.addImm(0);
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RS->enterBasicBlockEnd(MBB);
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Register Scav = RS->scavengeRegisterBackwards(
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LoongArch::GPRRegClass, PCALAU12I.getIterator(), /*RestoreAfter=*/false,
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/*SPAdj=*/0, /*AllowSpill=*/false);
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if (Scav != LoongArch::NoRegister)
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RS->setRegUsed(Scav);
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else {
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// When there is no scavenged register, it needs to specify a register.
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// Specify t8 register because it won't be used too often.
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|
Scav = LoongArch::R20;
|
|
int FrameIndex = LAFI->getBranchRelaxationSpillFrameIndex();
|
|
if (FrameIndex == -1)
|
|
report_fatal_error("The function size is incorrectly estimated.");
|
|
storeRegToStackSlot(MBB, PCALAU12I, Scav, /*IsKill=*/true, FrameIndex,
|
|
&LoongArch::GPRRegClass, TRI, Register());
|
|
TRI->eliminateFrameIndex(std::prev(PCALAU12I.getIterator()),
|
|
/*SpAdj=*/0, /*FIOperandNum=*/1);
|
|
PCALAU12I.getOperand(1).setMBB(&RestoreBB);
|
|
ADDI.getOperand(2).setMBB(&RestoreBB);
|
|
loadRegFromStackSlot(RestoreBB, RestoreBB.end(), Scav, FrameIndex,
|
|
&LoongArch::GPRRegClass, TRI, Register());
|
|
TRI->eliminateFrameIndex(RestoreBB.back(),
|
|
/*SpAdj=*/0, /*FIOperandNum=*/1);
|
|
}
|
|
MRI.replaceRegWith(ScratchReg, Scav);
|
|
MRI.clearVirtRegs();
|
|
}
|
|
|
|
static unsigned getOppositeBranchOpc(unsigned Opc) {
|
|
switch (Opc) {
|
|
default:
|
|
llvm_unreachable("Unrecognized conditional branch");
|
|
case LoongArch::BEQ:
|
|
return LoongArch::BNE;
|
|
case LoongArch::BNE:
|
|
return LoongArch::BEQ;
|
|
case LoongArch::BEQZ:
|
|
return LoongArch::BNEZ;
|
|
case LoongArch::BNEZ:
|
|
return LoongArch::BEQZ;
|
|
case LoongArch::BCEQZ:
|
|
return LoongArch::BCNEZ;
|
|
case LoongArch::BCNEZ:
|
|
return LoongArch::BCEQZ;
|
|
case LoongArch::BLT:
|
|
return LoongArch::BGE;
|
|
case LoongArch::BGE:
|
|
return LoongArch::BLT;
|
|
case LoongArch::BLTU:
|
|
return LoongArch::BGEU;
|
|
case LoongArch::BGEU:
|
|
return LoongArch::BLTU;
|
|
}
|
|
}
|
|
|
|
bool LoongArchInstrInfo::reverseBranchCondition(
|
|
SmallVectorImpl<MachineOperand> &Cond) const {
|
|
assert((Cond.size() && Cond.size() <= 3) && "Invalid branch condition!");
|
|
Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
|
|
return false;
|
|
}
|
|
|
|
std::pair<unsigned, unsigned>
|
|
LoongArchInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
|
|
return std::make_pair(TF, 0u);
|
|
}
|
|
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
|
LoongArchInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
|
|
using namespace LoongArchII;
|
|
// TODO: Add more target flags.
|
|
static const std::pair<unsigned, const char *> TargetFlags[] = {
|
|
{MO_CALL, "loongarch-call"},
|
|
{MO_CALL_PLT, "loongarch-call-plt"},
|
|
{MO_PCREL_HI, "loongarch-pcrel-hi"},
|
|
{MO_PCREL_LO, "loongarch-pcrel-lo"},
|
|
{MO_PCREL64_LO, "loongarch-pcrel64-lo"},
|
|
{MO_PCREL64_HI, "loongarch-pcrel64-hi"},
|
|
{MO_GOT_PC_HI, "loongarch-got-pc-hi"},
|
|
{MO_GOT_PC_LO, "loongarch-got-pc-lo"},
|
|
{MO_GOT_PC64_LO, "loongarch-got-pc64-lo"},
|
|
{MO_GOT_PC64_HI, "loongarch-got-pc64-hi"},
|
|
{MO_LE_HI, "loongarch-le-hi"},
|
|
{MO_LE_LO, "loongarch-le-lo"},
|
|
{MO_LE64_LO, "loongarch-le64-lo"},
|
|
{MO_LE64_HI, "loongarch-le64-hi"},
|
|
{MO_IE_PC_HI, "loongarch-ie-pc-hi"},
|
|
{MO_IE_PC_LO, "loongarch-ie-pc-lo"},
|
|
{MO_IE_PC64_LO, "loongarch-ie-pc64-lo"},
|
|
{MO_IE_PC64_HI, "loongarch-ie-pc64-hi"},
|
|
{MO_DESC_PC_HI, "loongarch-desc-pc-hi"},
|
|
{MO_DESC_PC_LO, "loongarch-desc-pc-lo"},
|
|
{MO_DESC64_PC_LO, "loongarch-desc64-pc-lo"},
|
|
{MO_DESC64_PC_HI, "loongarch-desc64-pc-hi"},
|
|
{MO_DESC_LD, "loongarch-desc-ld"},
|
|
{MO_DESC_CALL, "loongarch-desc-call"},
|
|
{MO_LD_PC_HI, "loongarch-ld-pc-hi"},
|
|
{MO_GD_PC_HI, "loongarch-gd-pc-hi"}};
|
|
return ArrayRef(TargetFlags);
|
|
}
|
|
|
|
// Returns true if this is the sext.w pattern, addi.w rd, rs, 0.
|
|
bool LoongArch::isSEXT_W(const MachineInstr &MI) {
|
|
return MI.getOpcode() == LoongArch::ADDI_W && MI.getOperand(1).isReg() &&
|
|
MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0;
|
|
}
|