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llvm-project/llvm/lib/Target/RISCV
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Craig Topper f0e79db215 [RISCV] Fix 80 columns in RISCVMatInt.cpp. NFC
2024-05-15 09:28:11 -07:00
..
AsmParser
[RISCV] Only allow up to e64 in vsetvli (#92010)
2024-05-14 10:11:20 -07:00
Disassembler
[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)
2024-04-29 10:11:28 -07:00
GISel
[RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (#89602)
2024-05-09 09:18:10 -04:00
MCA
[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc
2024-04-24 09:29:20 -07:00
MCTargetDesc
[RISCV] Fix 80 columns in RISCVMatInt.cpp. NFC
2024-05-15 09:28:11 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (#77770)
2024-02-26 12:12:31 +00:00
RISCV.h
Reapply "[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)"
2024-04-25 00:42:30 +08:00
RISCV.td
[RISCV] Add subtarget features for profiles
2024-04-28 11:32:37 +08:00
RISCVAsmPrinter.cpp
[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)
2024-04-23 15:12:36 -07:00
RISCVCallingConv.td
[RISCV] RISCV vector calling convention (1/2) (#77560)
2024-03-27 23:03:13 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.
2024-01-19 14:44:47 -08:00
RISCVCombine.td
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCVDeadRegisterDefinitions.cpp
[RISCV] Remove hasSideEffects=1 for vsetvli pseudos (#91319)
2024-05-15 23:37:31 +08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
RISCVFeatures.td
[RISCV] Add smstateen extension (#90818)
2024-05-02 09:12:44 -07:00
RISCVFoldMasks.cpp
[RISCV] Use DenseMap to track V0 definition. NFC (#84465)
2024-03-21 15:38:43 +08:00
RISCVFrameLowering.cpp
[RISCV] Add X27 to SavedRegs when X26 is in SavedRegs for cm.push/pop (#92067)
2024-05-14 08:06:10 -07:00
RISCVFrameLowering.h
[RISCV] Add CFI information for vector callee-saved registers (#86811)
2024-04-17 10:42:40 +08:00
RISCVGatherScatterLowering.cpp
[NFC][RemoveDIs] Use iterators for insertion at various call-sites (#84736)
2024-03-19 16:36:29 +00:00
RISCVGISel.td
[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825)
2023-12-04 13:00:34 -08:00
RISCVInsertReadWriteCSR.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVInsertVSETVLI.cpp
[RISCV] Move RISCVInsertVSETVLI to after phi elimination (#91440)
2024-05-15 11:44:32 +08:00
RISCVInsertWriteVXRM.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVInstrFormats.td
[RISCV] Rename OP-P to OP-VE. (#87546)
2024-04-05 17:02:03 -07:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrGISel.td
[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types
2024-04-03 15:27:15 -07:00
RISCVInstrInfo.cpp
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVInstrInfo.h
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVInstrInfo.td
[RISCV] Use software guarded branch for indirect jump table branch. (#66762)
2024-05-14 14:44:25 +08:00
RISCVInstrInfoA.td
[RISCV] Remove mayLoad = 1 from store-conditional (#88470)
2024-04-12 08:45:47 -07:00
RISCVInstrInfoC.td
[RISCV][NFC] Future-proof reference to ISA manual in RISCVInstrInfoC.td
2024-04-26 13:49:27 +01:00
RISCVInstrInfoD.td
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
RISCVInstrInfoF.td
[RISCV] Add casts to isel patterns that produce more than 1 instruction.
2024-02-08 23:38:19 -08:00
RISCVInstrInfoM.td
[RISCV] Split div vs rem scheduling information [nfc] (#84385)
2024-03-07 14:03:58 -08:00
RISCVInstrInfoSFB.td
[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945)
2024-02-07 16:03:30 +08:00
RISCVInstrInfoV.td
[RISCV] Model vd as a src for some Zvk* instructions in MC layer. (#86710)
2024-03-27 12:20:24 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove hasSideEffects=1 for vsetvli pseudos (#91319)
2024-05-15 23:37:31 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add codegen support for Zvfbfmin (#87911)
2024-05-07 10:25:06 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add codegen support for Zvfbfmin (#87911)
2024-05-07 10:25:06 +08:00
RISCVInstrInfoXCV.td
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVInstrInfoXSf.td
[RISCV] Add scheduling information for SiFive VCIX (#86093)
2024-04-16 13:55:45 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966)
2024-05-08 10:13:01 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZa.td
[RISCV][ISel] Add codegen support for the experimental zabha extension (#80192)
2024-02-16 15:35:09 +08:00
RISCVInstrInfoZalasr.td
[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
2024-02-01 10:58:21 -08:00
RISCVInstrInfoZb.td
[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966)
2024-05-08 10:13:01 -07:00
RISCVInstrInfoZc.td
[RISCV] Add validation of SPIMM for cm.push/pop. (#84989)
2024-03-28 08:38:18 -07:00
RISCVInstrInfoZcmop.td
[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)
2024-04-15 22:33:14 -07:00
RISCVInstrInfoZfa.td
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add casts to isel patterns that produce more than 1 instruction.
2024-02-08 23:38:19 -08:00
RISCVInstrInfoZicbo.td
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
RISCVInstrInfoZicfiss.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoZicond.td
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
RISCVInstrInfoZimop.td
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.
2023-08-04 09:08:16 -07:00
RISCVInstrInfoZvk.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVISelDAGToDAG.cpp
[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)
2024-05-14 19:08:04 +01:00
RISCVISelDAGToDAG.h
[RISCV] Improve constant materialisation for stores of i8 negative constants (#92131)
2024-05-14 19:08:04 +01:00
RISCVISelLowering.cpp
[RISCV] Fix a warning
2024-05-14 00:48:56 -07:00
RISCVISelLowering.h
[RISCV][CostModel] Add cost model for experimental.cttz.elts (#91778)
2024-05-14 09:18:08 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVMacroFusion.td
[RISCV] Use TableGen-based macro fusion (#72224)
2024-01-25 17:10:49 +08:00
RISCVMakeCompressible.cpp
[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375)
2024-03-27 13:40:38 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Merge ADDI with X0 into base offset (#78940)
2024-01-23 09:57:05 +08:00
RISCVMoveMerger.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVOptWInstrs.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Remove unnecessary initialization from RISCVPostRAExpandPseudo pass constructor.
2024-05-08 22:38:18 -07:00
RISCVProcessors.td
[RISCV] Remove extra indentation from RISCVProcessors.td.
2024-04-20 19:21:59 -07:00
RISCVProfiles.td
[TableGen][RISCV] Add initial support for marking profiles as experimental (#91993)
2024-05-14 05:34:39 +01:00
RISCVPushPopOptimizer.cpp
[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)
2024-02-07 14:30:45 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVRegisterInfo.cpp
[RISCV] Inogre CallingConv::RISCV_VectorCall in getCalleeSavedRegs if V/Zve is not enabled.
2024-05-13 16:04:09 -07:00
RISCVRegisterInfo.h
[RISCV] Store VLMul/NF into RegisterClass's TSFlags
2024-04-08 13:35:37 +08:00
RISCVRegisterInfo.td
[RISCV] Use software guarded branch for indirect jump table branch. (#66762)
2024-05-14 14:44:25 +08:00
RISCVSchedRocket.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedSiFive7.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedSiFiveP400.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedSiFiveP600.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedule.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVScheduleV.td
[RISCV] Fix typo in RISCVScheduleV.td that was introduced in 60a1158
2024-04-17 10:16:02 -07:00
RISCVScheduleXSf.td
[RISCV] Add scheduling information for SiFive VCIX (#86093)
2024-04-16 13:55:45 +08:00
RISCVScheduleZb.td
[RISCV] Add sched classes for Zbb integer min max instructions
2024-03-14 06:02:42 -07:00
RISCVScheduleZvk.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedXiangShanNanHu.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSubtarget.cpp
[RISCV] Use TableGen-based macro fusion (#72224)
2024-01-25 17:10:49 +08:00
RISCVSubtarget.h
[RISCV] Handle fixed length vectors with exact VLEN in lowerINSERT_SUBVECTOR (#84107)
2024-05-01 01:35:13 +08:00
RISCVSystemOperands.td
[RISCV] Add the CSR names from Smrnmi. (#83370)
2024-03-19 21:27:25 -07:00
RISCVTargetMachine.cpp
[RISCV] Move RISCVInsertVSETVLI to after phi elimination (#91440)
2024-05-15 11:44:32 +08:00
RISCVTargetMachine.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVTargetObjectFile.cpp
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
RISCVTargetObjectFile.h
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
RISCVTargetTransformInfo.cpp
[RISCV][CostModel] Add cost model for experimental.cttz.elts (#91778)
2024-05-14 09:18:08 -07:00
RISCVTargetTransformInfo.h
[TTI] getArithmeticInstrCost - use std:nullopt to create default empty ArrayRef<const Value *> Args argument. NFC.
2024-04-24 10:51:18 +01:00