6c412b6c6f
In [1], a few new insns are proposed to expand BPF ISA to
. fixing the limitation of existing insn (e.g., 16bit jmp offset)
. adding new insns which may improve code quality
(sign_ext_ld, sign_ext_mov, st)
. feature complete (sdiv, smod)
. better user experience (bswap)
This patch implemented insn encoding for
. sign-extended load
. sign-extended mov
. sdiv/smod
. bswap insns
. unconditional jump with 32bit offset
The new bswap insns are generated under cpu=v4 for __builtin_bswap.
For cpu=v3 or earlier, for __builtin_bswap, be or le insns are generated
which is not intuitive for the user.
To support 32-bit branch offset, a 32-bit ja (JMPL) insn is implemented.
For conditional branch which is beyond 16-bit offset, llvm will do
some transformation 'cond_jmp' -> 'cond_jmp + jmpl' to simulate 32bit
conditional jmp. See BPFMIPeephole.cpp for details. The algorithm is
hueristic based. I have tested bpf selftest pyperf600 with unroll account
600 which can indeed generate 32-bit jump insn, e.g.,
13: 06 00 00 00 9b cd 00 00 gotol +0xcd9b <LBB0_6619>
Eduard is working on to add 'st' insn to cpu=v4.
A list of llc flags:
disable-ldsx, disable-movsx, disable-bswap,
disable-sdiv-smod, disable-gotol
can be used to disable a particular insn for cpu v4.
For example, user can do:
llc -march=bpf -mcpu=v4 -disable-movsx t.ll
to enable cpu v4 without movsx insns.
References:
[1] https://lore.kernel.org/bpf/4bfe98be-5333-1c7e-2f6d-42486c8ec039@meta.com/
Differential Revision: https://reviews.llvm.org/D144829
126 lines
3.0 KiB
TableGen
126 lines
3.0 KiB
TableGen
//===-- BPFInstrFormats.td - BPF Instruction Formats -------*- tablegen -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class BPFOpClass<bits<3> val> {
|
|
bits<3> Value = val;
|
|
}
|
|
|
|
def BPF_LD : BPFOpClass<0x0>;
|
|
def BPF_LDX : BPFOpClass<0x1>;
|
|
def BPF_ST : BPFOpClass<0x2>;
|
|
def BPF_STX : BPFOpClass<0x3>;
|
|
def BPF_ALU : BPFOpClass<0x4>;
|
|
def BPF_JMP : BPFOpClass<0x5>;
|
|
def BPF_JMP32 : BPFOpClass<0x6>;
|
|
def BPF_ALU64 : BPFOpClass<0x7>;
|
|
|
|
class BPFSrcType<bits<1> val> {
|
|
bits<1> Value = val;
|
|
}
|
|
|
|
def BPF_K : BPFSrcType<0x0>;
|
|
def BPF_X : BPFSrcType<0x1>;
|
|
|
|
class BPFArithOp<bits<4> val> {
|
|
bits<4> Value = val;
|
|
}
|
|
|
|
def BPF_ADD : BPFArithOp<0x0>;
|
|
def BPF_SUB : BPFArithOp<0x1>;
|
|
def BPF_MUL : BPFArithOp<0x2>;
|
|
def BPF_DIV : BPFArithOp<0x3>;
|
|
def BPF_OR : BPFArithOp<0x4>;
|
|
def BPF_AND : BPFArithOp<0x5>;
|
|
def BPF_LSH : BPFArithOp<0x6>;
|
|
def BPF_RSH : BPFArithOp<0x7>;
|
|
def BPF_NEG : BPFArithOp<0x8>;
|
|
def BPF_MOD : BPFArithOp<0x9>;
|
|
def BPF_XOR : BPFArithOp<0xa>;
|
|
def BPF_MOV : BPFArithOp<0xb>;
|
|
def BPF_ARSH : BPFArithOp<0xc>;
|
|
def BPF_END : BPFArithOp<0xd>;
|
|
|
|
def BPF_XCHG : BPFArithOp<0xe>;
|
|
def BPF_CMPXCHG : BPFArithOp<0xf>;
|
|
|
|
class BPFEndDir<bits<1> val> {
|
|
bits<1> Value = val;
|
|
}
|
|
|
|
def BPF_TO_LE : BPFSrcType<0x0>;
|
|
def BPF_TO_BE : BPFSrcType<0x1>;
|
|
|
|
class BPFJumpOp<bits<4> val> {
|
|
bits<4> Value = val;
|
|
}
|
|
|
|
def BPF_JA : BPFJumpOp<0x0>;
|
|
def BPF_JEQ : BPFJumpOp<0x1>;
|
|
def BPF_JGT : BPFJumpOp<0x2>;
|
|
def BPF_JGE : BPFJumpOp<0x3>;
|
|
def BPF_JNE : BPFJumpOp<0x5>;
|
|
def BPF_JSGT : BPFJumpOp<0x6>;
|
|
def BPF_JSGE : BPFJumpOp<0x7>;
|
|
def BPF_CALL : BPFJumpOp<0x8>;
|
|
def BPF_EXIT : BPFJumpOp<0x9>;
|
|
def BPF_JLT : BPFJumpOp<0xa>;
|
|
def BPF_JLE : BPFJumpOp<0xb>;
|
|
def BPF_JSLT : BPFJumpOp<0xc>;
|
|
def BPF_JSLE : BPFJumpOp<0xd>;
|
|
|
|
class BPFWidthModifer<bits<2> val> {
|
|
bits<2> Value = val;
|
|
}
|
|
|
|
def BPF_W : BPFWidthModifer<0x0>;
|
|
def BPF_H : BPFWidthModifer<0x1>;
|
|
def BPF_B : BPFWidthModifer<0x2>;
|
|
def BPF_DW : BPFWidthModifer<0x3>;
|
|
|
|
class BPFModeModifer<bits<3> val> {
|
|
bits<3> Value = val;
|
|
}
|
|
|
|
def BPF_IMM : BPFModeModifer<0x0>;
|
|
def BPF_ABS : BPFModeModifer<0x1>;
|
|
def BPF_IND : BPFModeModifer<0x2>;
|
|
def BPF_MEM : BPFModeModifer<0x3>;
|
|
def BPF_MEMSX : BPFModeModifer<0x4>;
|
|
def BPF_ATOMIC : BPFModeModifer<0x6>;
|
|
|
|
class BPFAtomicFlag<bits<4> val> {
|
|
bits<4> Value = val;
|
|
}
|
|
|
|
def BPF_FETCH : BPFAtomicFlag<0x1>;
|
|
|
|
class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
: Instruction {
|
|
field bits<64> Inst;
|
|
field bits<64> SoftFail = 0;
|
|
let Size = 8;
|
|
|
|
let Namespace = "BPF";
|
|
let DecoderNamespace = "BPF";
|
|
|
|
BPFOpClass BPFClass;
|
|
let Inst{58-56} = BPFClass.Value;
|
|
|
|
dag OutOperandList = outs;
|
|
dag InOperandList = ins;
|
|
let AsmString = asmstr;
|
|
let Pattern = pattern;
|
|
}
|
|
|
|
// Pseudo instructions
|
|
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|
: InstBPF<outs, ins, asmstr, pattern> {
|
|
let Inst{63-0} = 0;
|
|
let isPseudo = 1;
|
|
}
|