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llvm-project/llvm/lib/Target/RISCV
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Shao-Ce SUN f48dab5237
Add RV64 constraint to SRLIW (#69416) 
Fixes #69408
2023-10-18 15:01:17 +08:00
..
AsmParser
[RISCV][MC] Recognise that fcvt.d.s with frm != 0b000 is valid (#67555)
2023-09-30 21:49:52 +01:00
Disassembler
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
GISel
[RISCV][GlobalISel] Select G_FRAME_INDEX (#68254)
2023-10-17 17:56:42 -07:00
MCA
[RISCV][llvm-mca] Fix Fix getLMUL values
2023-09-05 09:34:47 -07:00
MCTargetDesc
Use llvm::endianness::{big,little,native} (NFC)
2023-10-12 21:21:45 -07:00
TargetInfo
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
CMakeLists.txt
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCV.h
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCV.td
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVAsmPrinter.cpp
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
RISCVCallingConv.td
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVCombine.td
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add more instructions for the short forward branch optimization. (#66789)
2023-09-19 10:21:39 -07:00
RISCVFeatures.td
[RISCV] Make PostRAScheduler a target feature (#68692)
2023-10-11 10:51:03 +08:00
RISCVFrameLowering.cpp
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVFrameLowering.h
[llvm] Fix duplicate word typos. NFC
2023-09-01 18:25:16 -07:00
RISCVGatherScatterLowering.cpp
[RISCV] Match constant indices of non-index type when forming strided ops (#65777)
2023-09-18 09:41:34 -07:00
RISCVGISel.td
[RISCV][GISel] Add isel patterns for ADDIW/SRLIW/SRAIW/SLLIW and remove custom selection. (#68470)
2023-10-13 14:44:17 -07:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Separate hasRoundModeOpNum into separate VXRM and FRM functions.
2023-08-21 10:00:23 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
RISCVInstrFormats.td
[RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value of PseudoFloatLoad (#67014)
2023-09-23 01:21:28 +08:00
RISCVInstrFormatsC.td
[RISCV] Remove unused Opcode field from RVInst16. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrFormatsV.td
[RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC
2023-07-20 08:18:06 -07:00
RISCVInstrInfo.cpp
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
RISCVInstrInfo.h
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
RISCVInstrInfo.td
[RISCV][NFC] Remove space
2023-10-16 11:58:17 +08:00
RISCVInstrInfoA.td
[RISCV] Fix bad isel predicate handling for Ztso. (#66739)
2023-09-19 08:57:49 -07:00
RISCVInstrInfoC.td
[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)
2023-10-14 08:12:46 -07:00
RISCVInstrInfoD.td
[RISCV] Simplify PatSetCC_m and PatFprFprDynFrm_m (#68562)
2023-10-10 11:34:50 +08:00
RISCVInstrInfoF.td
[RISCV] Simplify PatSetCC_m and PatFprFprDynFrm_m (#68562)
2023-10-10 11:34:50 +08:00
RISCVInstrInfoM.td
[NFC][RISCV] Rewrite TableGen files using named arguments
2023-07-20 17:17:49 +08:00
RISCVInstrInfoV.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoVPseudos.td
[RISCV][NFC] Use NFList in NFSet (#67517)
2023-09-28 10:39:11 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin
2023-09-27 14:53:14 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Relax vslide*_vl patterns to allow any mask. NFC (#68203)
2023-10-04 21:26:14 +01:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Rename CVROR, NFC
2023-08-20 16:36:03 +10:00
RISCVInstrInfoXSf.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoXTHead.td
[RISCV][NFC] Use named arguments in newly added changes
2023-08-10 17:14:13 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZb.td
[RISCV][NFC] Remove mention of experimental extensions from RISCVInstrInfoZb.td header
2023-10-10 16:38:42 +01:00
RISCVInstrInfoZc.td
[RISCV][NFC] Correct RISCVInstrInfoZc.td header comment - Zc* extensions no longer experimental
2023-10-10 16:41:27 +01:00
RISCVInstrInfoZfa.td
[RISCV] Mark the Zfa extension as non-experimental (#68113)
2023-10-03 18:16:13 +01:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove trailing whitespace from some .td files.
2023-08-11 12:29:20 -07:00
RISCVInstrInfoZfh.td
[RISCV] Simplify PatSetCC_m and PatFprFprDynFrm_m (#68562)
2023-10-10 11:34:50 +08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZicond.td
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
[RISCV] Model all 3 arithmetic sources of vector FMA at MC layer.
2023-08-04 09:08:16 -07:00
RISCVInstrInfoZvk.td
[RISCV] Relax some Zvbb patterns and lowerings to Zvkb (#68115)
2023-10-03 17:42:40 +01:00
RISCVISelDAGToDAG.cpp
Add RV64 constraint to SRLIW (#69416)
2023-10-18 15:01:17 +08:00
RISCVISelDAGToDAG.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVISelLowering.cpp
[RISCV] Use separate CCValAssign for both parts of f64 with ilp32. (#69129)
2023-10-17 08:29:50 -07:00
RISCVISelLowering.h
[RISCV] Use vwsll.vi/vx + vwaddu.wv to lower vector.interleave when Zvbb enabled. (#67521)
2023-09-28 09:10:03 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVMacroFusion.cpp
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMacroFusion.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVMakeCompressible.cpp
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
2023-05-16 09:10:49 +01:00
RISCVMergeBaseOffset.cpp
[RISCV] Teach RISCVMergeBaseOffset to handle BlockAddress
2023-09-18 11:47:14 +08:00
RISCVMoveMerger.cpp
[RISCV][NFC] Adjust RISCVMoveMerge.cpp header to match standard style
2023-06-27 13:35:41 +01:00
RISCVOptWInstrs.cpp
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
RISCVProcessors.td
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
RISCVPushPopOptimizer.cpp
[RISCV][NFC] Correct/clarify RISCVPushPopOptimizer.cpp header comment
2023-10-10 16:50:15 +01:00
RISCVRedundantCopyElimination.cpp
[RISCV] Replace RISCV->RISC-V in strings.
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.cpp
[llvm] Remove SmallSet from MachineInstr.h
2023-08-12 18:15:27 +01:00
RISCVRegisterInfo.h
[RISCV] Replace RISCV -> RISC-V in comments. NFC
2023-03-27 09:50:17 -07:00
RISCVRegisterInfo.td
[RISCV][NFC] Use NFList in NFSet (#67517)
2023-09-28 10:39:11 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
RISCVSchedRocket.td
[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
2023-08-24 19:21:36 -07:00
RISCVSchedSiFive7.td
[RISCV] Fix SiFive7 formula for Reductions and ordered Reductions (#65385)
2023-09-05 23:04:21 -04:00
RISCVSchedSyntacoreSCR1.td
[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics
2023-08-24 19:21:36 -07:00
RISCVSchedule.td
[RISCV] Remove WriteJmpReg. Use WriteJalr in its place.
2023-06-25 21:59:27 -07:00
RISCVScheduleV.td
[RISCV] Add SchedRead for Merge operands on MASK Pseudos
2023-07-26 10:57:07 -07:00
RISCVScheduleZb.td
[RISCV] Split BEXT and BEXTI Write classes. NFC.
2023-07-17 15:52:40 -07:00
RISCVSubtarget.cpp
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
RISCVSubtarget.h
[RISCV] Make PostRAScheduler a target feature (#68692)
2023-10-11 10:51:03 +08:00
RISCVSystemOperands.td
[RISCV] Add support for custom CSRs for Sifive S76.
2023-07-14 09:51:15 -07:00
RISCVTargetMachine.cpp
[RISCV] Add sink-and-fold support for RISC-V. (#67602)
2023-10-07 10:38:35 -07:00
RISCVTargetMachine.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVTargetObjectFile.cpp
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetObjectFile.h
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
RISCVTargetTransformInfo.cpp
[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.
2023-10-05 06:17:07 -07:00
RISCVTargetTransformInfo.h
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
2023-09-25 12:26:01 +03:00