David Green 8a701024f3 [ARM] Lower i1 concat via MVETRUNC ...

The MVETRUNC operation can perform the same truncate of two vectors, without
requiring lane inserts/extracts from every vector lane. This moves the concat
i1 lowering to use it for v8i1 and v16i1 result types, trading a bit of extra
stack space for less instructions.

2023-10-18 19:40:11 +01:00

..

AArch64

[SVE ACLE] Allow default zero initialisation for svcount_t. (#69321)

2023-10-18 10:40:07 +01:00

AMDGPU

[AMDGPU] Add missing test checks. NFC. (#69484)

2023-10-18 11:26:39 -07:00

ARC

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ARM

[ARM] Lower i1 concat via MVETRUNC

2023-10-18 19:40:11 +01:00

AVR

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

BPF

Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"

2023-10-16 12:17:24 +02:00

CSKY

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

DirectX

[SPIRV][DX] Share one test between backends (#65975)

2023-09-21 12:15:55 +02:00

Generic

[AsmPrint] Correctly factor function entry count when dumping MBB frequencies (#67826)

2023-09-29 18:06:53 -07:00

Hexagon

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

Inputs

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Lanai

[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=

2023-09-11 15:11:01 -07:00

LoongArch

[LoongArch] Precommit a test for atomic cmpxchg optmization

2023-10-17 22:29:51 +08:00

M68k

[M68k] Add new calling convention M68k_RTD

2023-10-15 16:12:31 -07:00

Mips

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

MIR

[YAMLParser] Improve plain scalar spec compliance (#68946)

2023-10-17 11:28:14 -06:00

MLRegAlloc

[mlgo] Fix tests post 760e7d0

2023-10-17 12:19:54 -07:00

MSP430

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

NVPTX

[NVPTX] Fixed few more corner cases for v4i8 lowering. (#69263)

2023-10-17 11:06:11 -07:00

PowerPC

[PowerPC] Auto gen test checks for #69299. NFC.

2023-10-18 02:21:22 +00:00

RISCV

Add RV64 constraint to SRLIW (#69416)

2023-10-18 15:01:17 +08:00

SPARC

[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)

2023-10-10 20:34:20 +03:00

SPIRV

[SPIRV] Fix SPV_KHR_expect_assume support (#67793)

2023-10-09 10:05:58 +02:00

SystemZ

[SystemZ] Support builtin_{frame,return}_address() with non-zero argument (#69405)

2023-10-18 19:05:31 +02:00

Thumb

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

Thumb2

[ARM] Lower i1 concat via MVETRUNC

2023-10-18 19:40:11 +01:00

VE

Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"

2023-10-09 12:31:32 +01:00

WebAssembly

Ensure NoTrapAfterNoreturn is false for the wasm backend (#65876)

2023-10-05 09:17:45 -07:00

WinCFGuard

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WinEH

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X86

[DAGCombiner] Transform (icmp eq/ne (and X,C0),(shift X,C1)) to use rotate or to getter constants.

2023-10-18 01:16:55 -05:00

XCore

[test] Change llc -march= to -mtriple=

2023-09-11 14:42:37 -07:00