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llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
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Florian Hahn 38f8b7cbe4
[LV] Replace value numbers with patterns in tests (NFC). 
Replace some hardcoded value numbers in CHECK-LINES to use patterns, to
 make the tests more robust wrt renumbering.
2023-10-16 19:53:44 +01:00
..
defaults.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
divrem.ll
[LV] Use IRBuilder to create and optimize middle-block compare.
2023-08-29 11:42:18 +01:00
force-vect-msg.ll
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
2023-09-25 12:26:01 +03:00
illegal-type.ll
Recommit "[LV] Re-use existing broadcast value for live-ins."
2023-08-01 15:54:02 +01:00
inloop-reduction.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
interleaved-accesses-zve32x.ll
…
interleaved-accesses.ll
[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.
2023-10-05 06:17:07 -07:00
interleaved-cost.ll
[RISCV] Account for LMUL in memory op costs
2023-04-05 07:58:56 -07:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
lmul.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
low-trip-count.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
mask-index-type.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
masked_gather_scatter.ll
Regenerate test checks for tests affected by D141060
2023-10-04 10:51:35 -07:00
ordered-reduction.ll
…
reg-usage.ll
…
riscv-interleaved.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
riscv-unroll.ll
[LV] Optimize trip count SCEV.
2023-04-12 16:17:58 -07:00
riscv-vector-reverse.ll
[LV] Replace value numbers with patterns in tests (NFC).
2023-10-16 19:53:44 +01:00
safe-dep-distance.ll
[LV] Use IRBuilder to create and optimize middle-block compare.
2023-08-29 11:42:18 +01:00
scalable-basics.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
scalable-reductions.ll
[IR] llvm::createMinMaxOp - create integer min/max intrinsics instead of icmp/sel
2023-04-13 16:40:43 +01:00
scalable-tailfold.ll
[NFC][LoopVectorize] Change trip counts for some tests to guarantee a scalar tail
2023-03-24 09:43:50 +00:00
scalable-vf-hint.ll
…
select-cmp-reduction.ll
[LoopVectorize] Convert most tests to opaque pointers (NFC)
2023-06-12 13:10:22 +02:00
short-trip-count.ll
[AArch64] [LoopVectorize] Use either fixed-width or scalable VF when tail-folding (#67543)
2023-10-05 10:24:30 +01:00
strided-accesses.ll
[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)
2023-09-25 12:26:01 +03:00
uniform-load-store.ll
[LV] Use IRBuilder to create and optimize middle-block compare.
2023-08-29 11:42:18 +01:00
unroll-in-loop-vectorizer.ll
…
zvl32b.ll
[RISCV] Account for LMUL in memory op costs
2023-04-05 07:58:56 -07:00