d86047cb66
This patch prefixes tile slice layout with `layout` in the assemblyFormat: - `<vertical>` -> `layout<vertical>` - `<horizontal>` -> `layout<horizontal>` The reason for this change is the current format doesn't play nicely with additional optional operands, required to support padding and masking (#69148), as it becomes ambiguous. This affects the the following ops: - arm_sme.tile_load - arm_sme.tile_store - arm_sme.load_tile_slice - arm_sme.store_tile_slice
288 lines
11 KiB
C++
288 lines
11 KiB
C++
//===- ArmSMEToSCF.cpp - Convert ArmSME to SCF dialect ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements lowering of ArmSME operations to SCF.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/ArmSMEToSCF/ArmSMEToSCF.h"
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#include "mlir/Dialect/Arith/IR/Arith.h"
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#include "mlir/Dialect/ArmSME/IR/ArmSME.h"
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#include "mlir/Dialect/ArmSME/Utils/Utils.h"
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#include "mlir/Dialect/SCF/IR/SCF.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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namespace mlir {
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#define GEN_PASS_DEF_CONVERTARMSMETOSCF
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#include "mlir/Conversion/Passes.h.inc"
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} // namespace mlir
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using namespace mlir;
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namespace {
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/// Adjusts `indices` as follows for a given tile slice and returns them in
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/// `outIndices`:
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/// rank 1: (indices[0] + (tileSliceIndex * tileSliceNumElts))
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/// rank 2: (indices[0] + tileSliceIndex, indices[1])
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void getMemrefIndices(ValueRange indices, unsigned rank, Value tileSliceIndex,
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Value tileSliceNumElts,
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SmallVectorImpl<Value> &outIndices, Location loc,
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PatternRewriter &rewriter) {
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assert((rank == 1 || rank == 2) && "memref has unexpected rank!");
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auto tileSliceOffset = tileSliceIndex;
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if (rank == 1)
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tileSliceOffset =
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rewriter.create<arith::MulIOp>(loc, tileSliceOffset, tileSliceNumElts);
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auto baseIndexPlusTileSliceOffset =
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rewriter.create<arith::AddIOp>(loc, indices[0], tileSliceOffset);
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outIndices.push_back(baseIndexPlusTileSliceOffset);
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if (rank == 2)
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outIndices.push_back(indices[1]);
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}
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/// Lower `arm_sme.tile_load` to a loop over the tile slices and load each slice
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/// using `arm_sme.load_tile_slice`.
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///
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/// BEFORE:
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/// ```mlir
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/// %tile = arm_sme.tile_load %src[%c0, %c0] :
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/// memref<?x?xi32>, vector<[4]x[4]xi32>
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/// ```
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///
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/// AFTER:
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/// ```mlir
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/// %tile_id = arm_sme.get_tile_id : i32
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/// %tile = arm_sme.cast_tile_to_vector %tile_id : i32 to vector<[4]x[4]xi32>
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/// %vscale = vector.vscale
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/// %c0 = arith.constant 0 : index
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/// %c1 = arith.constant 1 : index
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/// %min_svl_s = arith.constant 4 : index
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/// %svl_s = arith.muli %min_svl_s, %vscale : index
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/// scf.for %tile_slice_idx = %c0 to %svl_s step %c1 {
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/// %tile_update = arm_sme.load_tile_slice %src[%tile_slice_idx],
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/// %tile, %tile_slice_idx : memref<?x?xi32>, vector<[4]x[4]xi32>
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/// }
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/// ```
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struct TileLoadOpConversion : public OpRewritePattern<arm_sme::TileLoadOp> {
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using OpRewritePattern<arm_sme::TileLoadOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(arm_sme::TileLoadOp tileLoadOp,
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PatternRewriter &rewriter) const override {
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OpBuilder::InsertionGuard g(rewriter);
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auto loc = tileLoadOp.getLoc();
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auto tileType = tileLoadOp.getVectorType();
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auto tileElementType = tileType.getElementType();
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unsigned tileElementWidth = tileElementType.getIntOrFloatBitWidth();
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// Create 'arm_sme.get_tile' op.
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auto tileId = rewriter.create<arm_sme::GetTileID>(
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loc, rewriter.getIntegerType(tileElementWidth));
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// Create `arm_sme.cast_tile_to_vector` to cast tile ID to a vector type to
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// use as input tile to 'arm_sme.load_tile_slice' ops.
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auto tile =
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rewriter.create<arm_sme::CastTileToVector>(loc, tileType, tileId);
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// Create a loop that loads each ZA tile slice from memory.
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auto step = rewriter.create<arith::ConstantIndexOp>(loc, 1);
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auto minTileSlices = rewriter.create<arith::ConstantIndexOp>(
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loc, arm_sme::getSMETileSliceMinNumElts(tileElementType));
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auto vscale =
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rewriter.create<vector::VectorScaleOp>(loc, rewriter.getIndexType());
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auto lowerBound = rewriter.create<arith::ConstantIndexOp>(loc, 0);
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// This describes both the number of ZA tile slices and the number of
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// elements in a vector of SVL bits for a given element type (SVL_B, SVL_H,
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// ..., SVL_Q).
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auto numTileSlices =
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rewriter.create<arith::MulIOp>(loc, minTileSlices, vscale);
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auto forOp =
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rewriter.create<scf::ForOp>(loc, lowerBound, numTileSlices, step);
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rewriter.setInsertionPointToStart(forOp.getBody());
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// Create 'arm_sme.load_tile_slice' to load tile slice from memory into
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// tile.
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SmallVector<Value> memrefIndices;
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auto tileSliceIndex = forOp.getInductionVar();
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getMemrefIndices(tileLoadOp.getIndices(),
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tileLoadOp.getMemRefType().getRank(), tileSliceIndex,
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numTileSlices, memrefIndices, loc, rewriter);
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rewriter.create<arm_sme::LoadTileSliceOp>(
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loc, tileType, tileLoadOp.getBase(), tile, memrefIndices,
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tileSliceIndex, tileLoadOp.getLayout());
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rewriter.setInsertionPointAfter(forOp);
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// Replace 'arm_sme.tile_load' with the tile.
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rewriter.replaceOp(tileLoadOp, tile);
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return success();
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}
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};
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/// Lower `arm_sme.tile_store` to a loop over the tile slices and store each
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/// slice using `arm_sme.store_tile_slice`.
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///
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/// BEFORE:
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/// ```mlir
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/// arm_sme.tile_store %tile, %dest[%c0, %c0] layout<vertical>
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/// : memref<?x?xi32>, vector<[4]x[4]xi32
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/// ```
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///
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/// AFTER:
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/// ```mlir
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/// %vscale = vector.vscale
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/// %c0 = arith.constant 0 : index
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/// %c1 = arith.constant 1 : index
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/// %min_svl_s = arith.constant 4 : index
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/// %svl_s = arith.muli %min_svl_s, %vscale : index
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/// scf.for %tile_slice_idx = %c0 to %svl_s step %c1 {
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/// arm_sme.store_tile_slice %tile, %tile_slice_idx, %dest[%tile_slice_idx],
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/// layout<vertical> : memref<?x?xi32>, vector<[4]x[4]xi32>
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/// }
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/// ```
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struct TileStoreOpConversion : public OpRewritePattern<arm_sme::TileStoreOp> {
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using OpRewritePattern<arm_sme::TileStoreOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(arm_sme::TileStoreOp tileStoreOp,
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PatternRewriter &rewriter) const override {
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OpBuilder::InsertionGuard g(rewriter);
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auto loc = tileStoreOp.getLoc();
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auto tileType = tileStoreOp.getVectorType();
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auto tileElementType = tileType.getElementType();
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// Create a loop that stores each ZA tile slice from memory.
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auto step = rewriter.create<arith::ConstantIndexOp>(loc, 1);
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auto minTileSlices = rewriter.create<arith::ConstantIndexOp>(
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loc, arm_sme::getSMETileSliceMinNumElts(tileElementType));
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auto vscale =
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rewriter.create<vector::VectorScaleOp>(loc, rewriter.getIndexType());
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auto lowerBound = rewriter.create<arith::ConstantIndexOp>(loc, 0);
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// This describes both the number of ZA tile slices and the number of
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// elements in a vector of SVL bits for a given element type (SVL_B, SVL_H,
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// ..., SVL_Q).
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auto numTileSlices =
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rewriter.create<arith::MulIOp>(loc, minTileSlices, vscale);
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auto forOp =
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rewriter.create<scf::ForOp>(loc, lowerBound, numTileSlices, step);
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rewriter.setInsertionPointToStart(forOp.getBody());
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SmallVector<Value> memrefIndices;
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auto tileSliceIndex = forOp.getInductionVar();
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getMemrefIndices(tileStoreOp.getIndices(),
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tileStoreOp.getMemRefType().getRank(), tileSliceIndex,
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numTileSlices, memrefIndices, loc, rewriter);
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rewriter.replaceOpWithNewOp<arm_sme::StoreTileSliceOp>(
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tileStoreOp, tileStoreOp.getValueToStore(), tileSliceIndex,
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tileStoreOp.getBase(), memrefIndices, tileStoreOp.getLayout());
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return success();
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}
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};
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/// Lowers `vector.print` of a tile into a loop over the rows of the tile,
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/// extracting them via `arm_sme.move_tile_slice_to_vector`, then printing with
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/// a 1D `vector.print`.
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///
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/// BEFORE:
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/// ```mlir
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/// vector.print %tile : vector<[4]x[4]xf32>
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/// ```
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/// AFTER:
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/// ```mlir
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/// %c0 = arith.constant 0 : index
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/// %c1 = arith.constant 1 : index
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/// %c4 = arith.constant 4 : index
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/// %vscale = vector.vscale
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/// %svl_s = arith.muli %c4, %vscale : index
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/// scf.for %i = %c0 to %svl_s step %c1 {
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/// %tile_slice = arm_sme.move_tile_slice_to_vector %tile[%i]
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/// : vector<[4]xf32> from vector<[4]x[4]xf32>
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/// vector.print %tile_slice : vector<[4]xf32>
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/// }
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/// ```
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struct TileVectorPrintOpConversion : public OpRewritePattern<vector::PrintOp> {
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using OpRewritePattern<vector::PrintOp>::OpRewritePattern;
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LogicalResult matchAndRewrite(vector::PrintOp printOp,
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PatternRewriter &rewriter) const override {
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if (!printOp.getSource())
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return failure();
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VectorType vectorType = dyn_cast<VectorType>(printOp.getPrintType());
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if (!vectorType || !arm_sme::isValidSMETileVectorType(vectorType))
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return failure();
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auto loc = printOp.getLoc();
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// Create a loop over the rows of the tile.
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auto vscale = rewriter.create<vector::VectorScaleOp>(loc);
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auto minTileRows =
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rewriter.create<arith::ConstantIndexOp>(loc, vectorType.getDimSize(0));
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auto lowerBound = rewriter.create<arith::ConstantIndexOp>(loc, 0);
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auto upperBound = rewriter.create<arith::MulIOp>(loc, minTileRows, vscale);
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auto step = rewriter.create<arith::ConstantIndexOp>(loc, 1);
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auto forOp = rewriter.create<scf::ForOp>(loc, lowerBound, upperBound, step);
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{
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// Loop body.
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rewriter.setInsertionPointToStart(forOp.getBody());
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// Extract the current row from the tile.
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Value rowIndex = forOp.getInductionVar();
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auto tileSlice = rewriter.create<arm_sme::MoveTileSliceToVectorOp>(
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loc, printOp.getSource(), rowIndex);
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// Print the row with a 1D vector.print.
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rewriter.create<vector::PrintOp>(loc, tileSlice,
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printOp.getPunctuation());
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}
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rewriter.eraseOp(printOp);
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return success();
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}
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};
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} // namespace
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void mlir::populateArmSMEToSCFConversionPatterns(RewritePatternSet &patterns) {
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patterns.add<TileLoadOpConversion, TileStoreOpConversion,
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TileVectorPrintOpConversion>(patterns.getContext());
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}
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namespace {
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struct ConvertArmSMEToSCFPass
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: public impl::ConvertArmSMEToSCFBase<ConvertArmSMEToSCFPass> {
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void runOnOperation() override {
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RewritePatternSet patterns(&getContext());
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ConversionTarget target(getContext());
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populateArmSMEToSCFConversionPatterns(patterns);
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target.addLegalDialect<arm_sme::ArmSMEDialect, vector::VectorDialect,
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arith::ArithDialect, scf::SCFDialect>();
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target.addIllegalOp<arm_sme::TileLoadOp, arm_sme::TileStoreOp>();
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target.addDynamicallyLegalOp<vector::PrintOp>([](vector::PrintOp op) {
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if (!op.getSource())
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return true;
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VectorType vectorType = dyn_cast<VectorType>(op.getPrintType());
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return !vectorType || !arm_sme::isValidSMETileVectorType(vectorType);
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});
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if (failed(applyPartialConversion(getOperation(), target,
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std::move(patterns))))
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signalPassFailure();
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}
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};
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} // namespace
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std::unique_ptr<Pass> mlir::createConvertArmSMEToSCFPass() {
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return std::make_unique<ConvertArmSMEToSCFPass>();
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}
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