40270e8ef2
Cover all the missing cases and add very detailed tests for each rule. In summary: - Flat and Scratch, addrspace(0) and addrspace(5), loads are always divergent. - Global and Constant, addrspace(1) and addrspace(4), have real uniform loads, s_load, but require additional checks for align and flags in mmo. For not natural align or not uniform mmo do uniform-in-vgpr lowering. - Private, addrspace(3), only has instructions for divergent load, for uniform do uniform-in-vgpr lowering. - Store rules are simplified using Ptr32 and Ptr64. All operands need to be vgpr. Some tests have code size regression since they use more sgpr instructions, marked with FixMe comment to get back to later.
19 lines
851 B
LLVM
19 lines
851 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -march=amdgcn -mtriple=amdgcn-amd-hmcsa -mcpu=gfx942 < %s | FileCheck -check-prefix=GFX942 %s
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define void @shuffle_to_extract(ptr addrspace(3) %in, ptr addrspace(3) %out) {
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; GFX942-LABEL: shuffle_to_extract:
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; GFX942: ; %bb.0:
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; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX942-NEXT: ds_read2_b64 v[2:5], v0 offset1:1
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; GFX942-NEXT: s_waitcnt lgkmcnt(0)
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; GFX942-NEXT: ds_write_b64 v1, v[4:5]
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; GFX942-NEXT: s_waitcnt lgkmcnt(0)
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; GFX942-NEXT: s_setpc_b64 s[30:31]
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%val = load <8 x half>, ptr addrspace(3) %in, align 8
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%res = shufflevector <8 x half> %val, <8 x half> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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store <4 x half> %res, ptr addrspace(3) %out, align 8
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ret void
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}
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