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llvm-project/llvm/test/CodeGen
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Hassnaa Hamdi 40a51e1afc [AArch64][SVE]: custom lower AVGFloor/AVGCeil. 
-Lower AVGFloor(A, B) to:
 SRL(A) + SRL(B) + (A&B)&1.
-Lower AVGCeil(A, B) to:
 SRL(A) + SRL(B) + (A|B)&1.

Differential Revision: https://reviews.llvm.org/D143283
2023-03-13 19:00:57 +00:00
..
AArch64
[AArch64][SVE]: custom lower AVGFloor/AVGCeil.
2023-03-13 19:00:57 +00:00
AMDGPU
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
ARC
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ARM
[ARM] Fix Chain/Glue Bug in PerformVMOVhrCombine
2023-03-06 11:55:54 +00:00
AVR
[AVR] Fix incorrect flags of livein registers when spilling them
2023-02-28 11:08:54 +08:00
BPF
[BPF] Improve pruning to avoid generate more types in BTF
2023-03-13 09:34:37 -07:00
CSKY
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DirectX
[NFC] Fix missing colon in CHECK directives
2023-02-21 00:13:04 +05:30
Generic
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Hexagon
[Passes] Remove some legacy passes
2023-03-10 17:17:00 -08:00
Inputs
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Lanai
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LoongArch
[llvm] add CallBrPrepare pass to pipelines
2023-02-16 17:58:34 -08:00
M68k
[M68k] Add support for basic memory constraints in inline asm
2023-03-08 13:52:34 -08:00
Mips
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
MIR
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MLRegalloc
Specify target triple for bb-prefix-dump.ll
2023-02-11 14:02:44 -08:00
MSP430
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NVPTX
[NVPTX] Sync generation of parameter names in a function signature with the function body.
2023-03-11 03:40:48 +01:00
PowerPC
Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5ef27753648396cac6ec
2023-03-12 21:59:18 -04:00
RISCV
Recommit "[RISCV] Add separate lookup tables for fli.h and fli.d."
2023-03-12 22:17:56 -07:00
SPARC
Revert "[SPARC] Lower BR_CC to BPr on 64-bit target whenever possible"
2023-03-12 04:20:25 -04:00
SPIRV
[SPIR-V] Support TargetExtType for SPIR-V builtin types
2023-02-27 21:39:25 +01:00
SystemZ
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Thumb
[LSR] Improve filtered uses in NarrowSearchSpaceByPickingWinnerRegs
2023-02-16 15:48:12 +00:00
Thumb2
[SCEV] Strengthen nowrap flags via ranges for ARs on construction.
2023-03-07 17:10:34 +01:00
VE
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
WebAssembly
[SelectionDAG] Fix mismatched truncate when combine BUILD_VECTOR with EXTRACT_SUBVECTOR
2023-03-13 08:59:52 +08:00
WinCFGuard
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WinEH
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X86
[X86] Use llvm::Align for passing the alignment
2023-03-14 00:06:21 +08:00
XCore
[XCore] Adapt threads.ll to opaque pointers.
2023-02-15 10:43:51 +00:00