4b414d9ade
Add the prefixed instructions pld and pstd to future CPU. These are load and store instructions that require new operand types that are 34 bits. This patch adds the two instructions as well as the operand types required. Note that this patch also makes a minor change to tablegen to account for the fact that some instructions are going to require shifts greater than 31 bits for the new 34 bit instructions. Differential Revision: https://reviews.llvm.org/D72574
81 lines
3.7 KiB
C++
81 lines
3.7 KiB
C++
//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCINSTPRINTER_H
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#define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCINSTPRINTER_H
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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class PPCInstPrinter : public MCInstPrinter {
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Triple TT;
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private:
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bool showRegistersWithPercentPrefix(const char *RegName) const;
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bool showRegistersWithPrefix() const;
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const char *getVerboseConditionRegName(unsigned RegNum,
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unsigned RegEncoding) const;
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public:
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PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, Triple T)
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: MCInstPrinter(MAI, MII, MRI), TT(T) {}
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
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const MCSubtargetInfo &STI, raw_ostream &O) override;
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
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void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx,
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raw_ostream &OS);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier = nullptr);
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void printATBitsAsHint(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS34ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printImmZeroOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegImm34(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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};
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} // end namespace llvm
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#endif
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