15bcc36eed
Move async copy operations to NVGPU as they only exist on NV target and are designed to match ptx semantic. This allows us to also add more fine grain caching hint attribute to the op. Add hint to bypass L1 and hook it up to NVVM op. Differential Revision: https://reviews.llvm.org/D125244
56 lines
2.0 KiB
MLIR
56 lines
2.0 KiB
MLIR
// RUN: mlir-opt -split-input-file -verify-diagnostics %s
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func.func @async_cp_memory_space(%dst : memref<16xf32>, %src : memref<16xf32>, %i : index) -> () {
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// expected-error @+1 {{destination memref must have memory space 3}}
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nvgpu.device_async_copy %src[%i], %dst[%i], 16 : memref<16xf32> to memref<16xf32>
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return
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}
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// -----
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func.func @async_cp_memref_type(%dst : memref<16xi32, 3>, %src : memref<16xf32>, %i : index) -> () {
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// expected-error @+1 {{source and destination must have the same element type}}
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nvgpu.device_async_copy %src[%i], %dst[%i], 16 : memref<16xf32> to memref<16xi32, 3>
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return
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}
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// -----
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func.func @async_cp_num_src_indices(%dst : memref<16xf32, 3>, %src : memref<16x16xf32>, %i : index) -> () {
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// expected-error @+1 {{expected 2 source indices, got 1}}
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nvgpu.device_async_copy %src[%i], %dst[%i], 16 : memref<16x16xf32> to memref<16xf32, 3>
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return
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}
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// -----
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func.func @async_cp_num_dst_indices(%dst : memref<16x16xf32, 3>, %src : memref<16xf32>, %i : index) -> () {
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// expected-error @+1 {{expected 2 destination indices, got 1}}
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nvgpu.device_async_copy %src[%i], %dst[%i], 16 : memref<16xf32> to memref<16x16xf32, 3>
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return
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}
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// -----
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func.func @async_cp_num_src_stride(
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%dst : memref<200x100xf32, 3>,
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%src : memref<200x100xf32, affine_map<(d0, d1) -> (200*d0 + 2*d1)>>,
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%i : index) -> () {
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// expected-error @+1 {{source memref most minor dim must have unit stride}}
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nvgpu.device_async_copy %src[%i, %i], %dst[%i, %i], 16 :
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memref<200x100xf32, affine_map<(d0, d1) -> (200*d0 + 2*d1)>> to memref<200x100xf32, 3>
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return
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}
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// -----
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func.func @async_cp_num_dst_stride(
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%dst : memref<200x100xf32, affine_map<(d0, d1) -> (200*d0 + 2*d1)>, 3>,
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%src : memref<200x100xf32>,
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%i : index) -> () {
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// expected-error @+1 {{destination memref most minor dim must have unit stride}}
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nvgpu.device_async_copy %src[%i, %i], %dst[%i, %i], 16 :
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memref<200x100xf32> to memref<200x100xf32, affine_map<(d0, d1) -> (200*d0 + 2*d1)>, 3>
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return
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}
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