Guy David 5e22597aa0

[AArch64] Verify consecutive vector registers in tbl, tbx (#120262) ...

Table lookup instructions expect the vectors that define the table
itself to be consecutive (wraparound allowed).
Relevant documentation:

https://developer.arm.com/documentation/100069/0606/SIMD-Vector-Instructions/TBL--vector-

2024-12-20 20:08:24 +02:00

..

AArch64AsmParser.cpp

[AArch64] Verify consecutive vector registers in tbl, tbx (#120262)

2024-12-20 20:08:24 +02:00

CMakeLists.txt

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