9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
52 lines
1.5 KiB
LLVM
52 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; GCN-LABEL: {{^}}add_var_var_i1:
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; GFX9: s_xor_b64
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; GFX10: s_xor_b32
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define amdgpu_kernel void @add_var_var_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
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%a = load volatile i1, ptr addrspace(1) %in0
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%b = load volatile i1, ptr addrspace(1) %in1
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%add = add i1 %a, %b
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store i1 %add, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}add_var_imm_i1:
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; GFX9: s_not_b64
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; GFX10: s_not_b32
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define amdgpu_kernel void @add_var_imm_i1(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%a = load volatile i1, ptr addrspace(1) %in
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%add = add i1 %a, 1
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store i1 %add, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}add_i1_cf:
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; GCN: ; %endif
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; GFX9: s_not_b64
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; GFX10: s_not_b32
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define amdgpu_kernel void @add_i1_cf(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%d_cmp = icmp ult i32 %tid, 16
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br i1 %d_cmp, label %if, label %else
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if:
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%0 = load volatile i1, ptr addrspace(1) %a
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br label %endif
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else:
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%1 = load volatile i1, ptr addrspace(1) %b
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br label %endif
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endif:
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%2 = phi i1 [%0, %if], [%1, %else]
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%3 = add i1 %2, -1
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store i1 %3, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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