9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
75 lines
2.8 KiB
LLVM
75 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: {{^}}flt_f64:
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; CHECK: v_cmp_nge_f64_e32 vcc, {{s\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @flt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fcmp ult double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}fle_f64:
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; CHECK: v_cmp_ngt_f64_e32 vcc, {{s\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fle_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fcmp ule double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}fgt_f64:
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; CHECK: v_cmp_nle_f64_e32 vcc, {{s\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fgt_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fcmp ugt double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}fge_f64:
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; CHECK: v_cmp_nlt_f64_e32 vcc, {{s\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fge_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fcmp uge double %r0, %r1
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%r3 = zext i1 %r2 to i32
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store i32 %r3, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}fne_f64:
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; CHECK: v_cmp_neq_f64_e32 vcc, {{s\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fne_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fcmp une double %r0, %r1
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%r3 = select i1 %r2, double %r0, double %r1
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store double %r3, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}feq_f64:
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; CHECK: v_cmp_nlg_f64_e32 vcc, {{s\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @feq_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fcmp ueq double %r0, %r1
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%r3 = select i1 %r2, double %r0, double %r1
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store double %r3, ptr addrspace(1) %out
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ret void
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}
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