9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GCN %s
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; GCN-LABEL: {{^}}s_input_output_i16:
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; GCN: s_mov_b32 s[[REG:[0-9]+]], -1
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; GCN: ; use s[[REG]]
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define amdgpu_kernel void @s_input_output_i16() #0 {
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%v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
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tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
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ret void
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}
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; GCN-LABEL: {{^}}v_input_output_i16:
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; GCN: v_mov_b32 v[[REG:[0-9]+]], -1
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; GCN: ; use v[[REG]]
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define amdgpu_kernel void @v_input_output_i16() #0 {
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%v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
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tail call void asm sideeffect "; use $0", "v"(i16 %v)
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ret void
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}
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; GCN-LABEL: {{^}}s_input_output_f16:
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; GCN: s_mov_b32 s[[REG:[0-9]+]], -1
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; GCN: ; use s[[REG]]
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define amdgpu_kernel void @s_input_output_f16() #0 {
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%v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0
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tail call void asm sideeffect "; use $0", "s"(half %v)
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ret void
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}
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; GCN-LABEL: {{^}}v_input_output_f16:
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; GCN: v_mov_b32 v[[REG:[0-9]+]], -1
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; GCN: ; use v[[REG]]
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define amdgpu_kernel void @v_input_output_f16() #0 {
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%v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
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tail call void asm sideeffect "; use $0", "v"(half %v)
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ret void
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}
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attributes #0 = { nounwind }
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