shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/DebugInfo/MIR/X86
History
Fangrui Song e339f0a9da [test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
..
avoid-single-entry-value-location.mir
…
backup-entry-values-usage.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
bit-piece-dh.mir
…
call-site-gnu-vs-dwarf5-attrs.mir
[DWARF] Don't emit DWARF5 symbols for DWARF2/3 + non-lldb (#110120)
2024-09-27 10:27:04 +08:00
call-site-param-mov16.mir
…
callsite-stack-value.mir
…
clobbered-fragments.mir
…
complex-entryvalue.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
dbg-call-site-spilled-arg-multiple-defs.mir
…
dbg-call-site-spilled-arg.mir
…
dbg-prologue-backup-loc2.mir
[DebugInfo] Handle trailing empty blocks when seeking prologue_end spot (#117320)
2024-11-26 14:24:25 +00:00
dbg-stack-value-range.mir
…
dbgcall-site-clobbered-regs.mir
…
dbgcall-site-copy-super-sub.mir
…
dbgcall-site-interpretation.mir
…
dbgcall-site-lea-interpretation.mir
…
dbgcall-site-partial-describe-subreg.mir
…
dbgcall-site-partial-describe.mir
…
dbgcall-site-reference.mir
…
dbgcall-site-reg-shuffle.mir
…
dbgcall-site-two-fwd-reg-defs.mir
…
dbginfo-entryvals.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
debug-call-site-param.mir
…
debug-entry-value-operation.mir
…
debug-loc-0.mir
…
dvl-livedebugvalues-clobber.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
dvl-livedebugvalues-join.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
dvl-livedebugvalues-movements.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
dvl-livedebugvalues-spillrestore.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
dvl-livedebugvars-movements.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
dvl-livedebugvars-stackptr.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
empty-inline.mir
Reapply ccddb6ffad1, "Emit a worst-case prologue_end"
2024-11-14 10:30:17 +00:00
entry-value-of-modified-param2.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
entry-value-of-modified-param.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
entry-values-diamond-bbs.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
instr-ref-join-def-vphi.mir
[DebugInfo,test] Convert text files from CRLF to LF
2024-05-03 09:51:56 -07:00
kill-after-spill.mir
…
kill-entry-value-after-diamond-bbs2.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
kill-entry-value-after-diamond-bbs.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
ldv_unreachable_blocks2.mir
…
ldv_unreachable_blocks.mir
…
lit.local.cfg
…
live-debug-values-3preds.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
live-debug-values-bad-transfer2.mir
…
live-debug-values-bad-transfer.mir
…
live-debug-values-cutoffs.mir
…
live-debug-values-entry-transfer.mir
…
live-debug-values-fragments.mir
Reapply 078198f310d5 "Index DebugVariables and some DILocations"
2024-07-18 15:55:06 +01:00
live-debug-values-reg-copy.mir
…
live-debug-values-restore-collide.mir
…
live-debug-values-restore.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
live-debug-values-spill.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
live-debug-values-stack-clobber.mir
…
live-debug-values.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
live-debug-vars-unused-arg-debugonly.mir
…
live-debug-vars-unused-arg.mir
…
livedebugvalues_basic_diamond_match_clobber.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_basic_diamond_match_move.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_basic_diamond_one_clobber.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_basic_diamond_one_move.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_basic_diamond.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_basic_loop.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_bb_to_bb_clobbered.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_bb_to_bb_move_to_clobber.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_bb_to_bb.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_load_in_loop.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_break_clobbered.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_break.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_clobbered.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_diamond_clobber.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_diamond_move.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_diamond.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_early_clobber.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_terminated.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_two_backedge_clobbered.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_two_backedge.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_within_loop_clobbered.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_within_loop_moved.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_within_loop_outer_moved.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_loop_within_loop.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues_many_loop_heads.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues-ignores-metaInstructions.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
livedebugvalues-limit.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
livedebugvars-crossbb-interval.mir
…
machine-cse.mir
Remove br i1 undef from some regression tests [NFC] (#115130)
2024-11-07 08:11:15 +00:00
machinesink-subreg.mir
…
machinesink.mir
…
merge-inline-loc1.mir
…
merge-inline-loc2.mir
…
merge-inline-loc3.mir
…
merge-inline-loc4.mir
…
mlicm-hoist-post-regalloc.mir
…
mlicm-hoist-pre-regalloc.mir
[CodeGen][NFC] Properly split MachineLICM and EarlyMachineLICM (#113573)
2024-10-25 11:19:22 -07:00
multiple-param-dbg-value-entry.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
no-cfi-loc.mir
[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
2024-12-15 11:23:08 -08:00
piece-entryval.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
postra-subreg-sink.mir
…
prolog-epilog-indirection.mir
…
propagate-entry-value-cross-bbs.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
regcoalescer.mir
…
regcoalescing-clears-dead-dbgvals.mir
…
remove-entry-value-from-loop.mir
[test] Remove redundant -march=x86-64 when target triple is specified in IR
2024-12-15 11:30:14 -08:00
remove-redundant-dbg-vals.mir
…
sink-leaves-undef.mir
…
unreachable-block-call-site.mir
…