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llvm-project
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llvm
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test
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tools
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llvm-mca
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RISCV
History
Min-Yih Hsu
90d79ca4c7
[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (
#122007
)
...
According to llvm-exegesis, they should have around 2 cycles of latency on P400 cores.
2025-01-07 15:01:05 -08:00
..
MIPS
Reland "[RISCV] Add scheduling model for mips p8700 CPU" (
#120550
)
2024-12-19 14:26:43 +01:00
SiFive7
[RISCV][MCA] Move sifive-x280 tests to directory SiFiveX280 (
#120522
)
2024-12-19 14:58:04 +08:00
SiFiveP400
[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model (
#122007
)
2025-01-07 15:01:05 -08:00
SiFiveP600
[RISCV] Mark vmvNr.v as implicitly using vtype (
#118414
)
2024-12-04 15:10:57 +08:00
SiFiveX280
[RISCV][MCA] Move sifive-x280 tests to directory SiFiveX280 (
#120522
)
2024-12-19 14:58:04 +08:00
SyntacoreSCR
[RISCV] Add scheduling model for Syntacore SCR7 (
#108814
)
2024-09-17 18:52:55 +03:00
tt-ascalon-d8
[RISC-V] Base scheduling model for tt-ascalon-d8 (
#120160
)
2024-12-20 15:30:17 -05:00
XiangShan
[RISCV] Add sched model for XiangShan-NanHu (
#70232
)
2024-02-12 15:00:54 +08:00
lit.local.cfg
…
